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OpenSTA
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This commit is contained in:
James Cherry 2019-08-12 22:56:32 -07:00
parent a20fb113b7
commit 41ebd34031
5 changed files with 30 additions and 13 deletions
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3
network/SdcNetwork.cc
View File

@ -595,6 +595,7 @@ SdcNetwork::findPort(const Cell *cell,
index); index);
port = network_->findPort(cell, escaped2); port = network_->findPort(cell, escaped2);
} }
stringDelete(bus_name);
} }
} }
return port; return port;
@ -624,6 +625,7 @@ SdcNetwork::findPortsMatching(const Cell *cell,
PatternMatch escaped_pattern2(escaped2, pattern); PatternMatch escaped_pattern2(escaped2, pattern);
network_->findPortsMatching(cell, &escaped_pattern2, ports); network_->findPortsMatching(cell, &escaped_pattern2, ports);
} }
stringDelete(bus_name);
} }
} }
} }
@ -814,6 +816,7 @@ SdcNetwork::findPin(const Instance *instance,
index); index);
pin = network_->findPin(instance, escaped2); pin = network_->findPin(instance, escaped2);
} }
stringDelete(bus_name);
} }
} }
return pin; return pin;

11
network/VerilogNamespace.cc
View File

@ -36,10 +36,13 @@ netVerilogName(const char *sta_name,
char *bus_name; char *bus_name;
int index; int index;
parseBusName(sta_name, '[', ']', bus_name, index); parseBusName(sta_name, '[', ']', bus_name, index);
if (bus_name) if (bus_name) {
return stringPrintTmp("%s[%d]", const char *vname = stringPrintTmp("%s[%d]",
staToVerilog(bus_name, escape), staToVerilog(bus_name, escape),
index); index);
stringDelete(bus_name);
return vname;
}
else else
return staToVerilog(sta_name, escape); return staToVerilog(sta_name, escape);
} }

8
search/Sim.cc
View File

@ -1021,6 +1021,12 @@ Sim::logicZeroOne(const Pin *pin) const
return logicValueZeroOne(logicValue(pin)); return logicValueZeroOne(logicValue(pin));
} }
bool
Sim::logicZeroOne(const Vertex *vertex) const
{
return logicValueZeroOne(vertex->simValue());
}
void void
Sim::clearSimValues() Sim::clearSimValues()
{ {
@ -1100,7 +1106,7 @@ Sim::annotateVertexEdges(const Instance *inst,
bool is_disabled_cond = false; bool is_disabled_cond = false;
if (annotate) { if (annotate) {
// Set timing sense on edges in instances that have constant pins. // Set timing sense on edges in instances that have constant pins.
if (logicZeroOne(from_pin)) if (logicZeroOne(from_vertex))
sense = TimingSense::none; sense = TimingSense::none;
else else
sense = functionSense(inst, from_pin, pin); sense = functionSense(inst, from_pin, pin);

1
search/Sim.hh
View File

@ -54,6 +54,7 @@ public:
const Instance *inst) const; const Instance *inst) const;
LogicValue logicValue(const Pin *pin) const; LogicValue logicValue(const Pin *pin) const;
bool logicZeroOne(const Pin *pin) const; bool logicZeroOne(const Pin *pin) const;
bool logicZeroOne(const Vertex *vertex) const;
// Timing sense for the function between from_pin and to_pin // Timing sense for the function between from_pin and to_pin
// after simplifying the function based constants on the pins. // after simplifying the function based constants on the pins.
virtual TimingSense functionSense(const Instance *inst, virtual TimingSense functionSense(const Instance *inst,

20
search/Sta.cc
View File

@ -1597,11 +1597,13 @@ Sta::isDisabledConstant(Edge *edge)
{ {
sim_->ensureConstantsPropagated(); sim_->ensureConstantsPropagated();
const TimingRole *role = edge->role(); const TimingRole *role = edge->role();
Pin *from_pin = edge->from(graph_)->pin(); Vertex *from_vertex = edge->from(graph_);
Pin *to_pin = edge->to(graph_)->pin(); Pin *from_pin = from_vertex->pin();
Vertex *to_vertex = edge->to(graph_);
Pin *to_pin = to_vertex->pin();
const Instance *inst = network_->instance(from_pin); const Instance *inst = network_->instance(from_pin);
return sim_->logicZeroOne(from_pin) return sim_->logicZeroOne(from_vertex)
|| sim_->logicZeroOne(to_pin) || sim_->logicZeroOne(to_vertex)
|| (!role->isWire() || (!role->isWire()
&& (isCondDisabled(edge, inst, from_pin, to_pin, network_, sim_) && (isCondDisabled(edge, inst, from_pin, to_pin, network_, sim_)
|| isModeDisabled(edge, inst, network_, sim_) || isModeDisabled(edge, inst, network_, sim_)
@ -1640,12 +1642,14 @@ Sta::disabledConstantPins(Edge *edge)
{ {
sim_->ensureConstantsPropagated(); sim_->ensureConstantsPropagated();
PinSet *pins = new PinSet; PinSet *pins = new PinSet;
Pin *from_pin = edge->from(graph_)->pin(); Vertex *from_vertex = edge->from(graph_);
Pin *to_pin = edge->to(graph_)->pin(); Pin *from_pin = from_vertex->pin();
if (sim_->logicZeroOne(from_pin)) Vertex *to_vertex = edge->to(graph_);
Pin *to_pin = to_vertex->pin();
if (sim_->logicZeroOne(from_vertex))
pins->insert(from_pin); pins->insert(from_pin);
if (edge->role()->isWire()) { if (edge->role()->isWire()) {
if (sim_->logicZeroOne(to_pin)) if (sim_->logicZeroOne(to_vertex))
pins->insert(to_pin); pins->insert(to_pin);
} }
else { else {