Initial Pass at Attribute parsing
This commit is contained in:
Ethan Mahintorabi
parent
2cfbeb4672
commit
414e4e44aa
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@ -6,9 +6,12 @@ TAGS
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.#*
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.~lock.*\.*#
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.DS_Store
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.vscode
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.idea
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Makefile
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gmon.out
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cmake-build-debug
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build
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pvt
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@ -0,0 +1,15 @@
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read_liberty sky130hd_tt.lib
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read_verilog attribute_parsing_test.v
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link_design counter
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create_clock -name clk [get_ports clk] -period 50
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set timing_paths [find_timing_paths -sort_by_slack]
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set critical_path [lindex $timing_paths 0]
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set critical_path_length [expr {- [get_property $critical_path slack]}]
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report_checks -format full
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puts stderr "Critical path length is $critical_path_length\n"
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set instance [sta::top_instance]
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set cell [$instance cell]
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set cell_name [$cell name]
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set src_location [$cell get_attribute "src"]
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puts "top_instance:\"$cell_name\" attribute \"src\" = $src_location \n"
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File diff suppressed because it is too large
Load Diff
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@ -38,6 +38,7 @@ class LibertyCell;
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class LibertyPort;
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typedef Map<const char*, ConcreteCell*, CharPtrLess> ConcreteCellMap;
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typedef Map<std::string, const char*> AttributeMap;
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typedef Vector<ConcretePort*> ConcretePortSeq;
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typedef Map<const char*, ConcretePort*, CharPtrLess> ConcretePortMap;
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typedef ConcreteCellMap::ConstIterator ConcreteLibraryCellIterator;
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@ -105,6 +106,8 @@ public:
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ConcreteCellPortBitIterator *portBitIterator() const;
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bool isLeaf() const { return is_leaf_; }
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void setIsLeaf(bool is_leaf);
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void setAttribute(const char *key, const char *value);
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const char *getAttribute(const char *key) const;
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// Cell acts as port factory.
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ConcretePort *makePort(const char *name);
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@ -158,6 +161,7 @@ protected:
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// Port bit count (expanded buses).
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int port_bit_count_;
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bool is_leaf_;
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AttributeMap attribute_map_;
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private:
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friend class ConcreteLibrary;
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@ -38,6 +38,7 @@ class ConcreteBindingTbl;
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class ConcreteLibertyLibraryIterator;
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typedef Vector<ConcreteLibrary*> ConcreteLibrarySeq;
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typedef Map<std::string, const char*> AttributeMap;
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typedef Map<const char*, ConcreteLibrary*, CharPtrLess> ConcreteLibraryMap;
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typedef ConcreteLibrarySeq::ConstIterator ConcreteLibraryIterator;
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typedef Map<const char *, ConcreteInstance*,
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@ -74,6 +75,7 @@ public:
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const PatternMatch *pattern) const override;
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const char *name(const Cell *cell) const override;
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const char *getAttribute(const Cell *cell, const char *key) const override;
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ObjectId id(const Cell *cell) const override;
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Library *library(const Cell *cell) const override;
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LibertyCell *libertyCell(Cell *cell) const override;
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@ -108,6 +110,7 @@ public:
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PortMemberIterator *memberIterator(const Port *port) const override;
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const char *name(const Instance *instance) const override;
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const char *getAttribute(const Instance *inst, const char *key) const override;
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ObjectId id(const Instance *instance) const override;
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Cell *cell(const Instance *instance) const override;
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Instance *parent(const Instance *instance) const override;
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@ -175,6 +178,9 @@ public:
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const char *name) override;
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void setIsLeaf(Cell *cell,
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bool is_leaf) override;
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void setAttribute(Cell *cell,
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const char *key,
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const char *value) override;
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Port *makePort(Cell *cell,
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const char *name) override;
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Port *makeBusPort(Cell *cell,
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@ -206,6 +212,9 @@ public:
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Pin *connect(Instance *inst,
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LibertyPort *port,
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Net *net) override;
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void setAttribute(Instance *inst,
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const char *key,
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const char *value) override;
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void disconnectPin(Pin *pin) override;
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void deletePin(Pin *pin) override;
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Net *makeNet(const char *name,
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@ -285,6 +294,8 @@ public:
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InstanceNetIterator *netIterator() const;
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Instance *findChild(const char *name) const;
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InstanceChildIterator *childIterator() const;
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void setAttribute(const char *key, const char *value);
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const char *getAttribute(const char *key) const;
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void addChild(ConcreteInstance *child);
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void deleteChild(ConcreteInstance *child);
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void addPin(ConcretePin *pin);
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@ -310,6 +321,7 @@ protected:
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ConcretePinSeq pins_;
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ConcreteInstanceChildMap *children_;
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ConcreteInstanceNetMap *nets_;
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AttributeMap attribute_map_;
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private:
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friend class ConcreteNetwork;
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@ -144,6 +144,8 @@ public:
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virtual Cell *cell(LibertyCell *cell) const = 0;
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// Filename may return null.
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virtual const char *filename(const Cell *cell) = 0;
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// Attributes can be null
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virtual const char *getAttribute(const Cell *cell, const char *key) const = 0;
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// Name can be a simple, bundle, bus, or bus bit name.
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virtual Port *findPort(const Cell *cell,
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const char *name) const = 0;
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@ -206,6 +208,7 @@ public:
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const PatternMatch *pattern) const;
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virtual InstanceSeq findInstancesHierMatching(const Instance *instance,
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const PatternMatch *pattern) const;
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virtual const char *getAttribute(const Instance *inst, const char *key) const = 0;
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// Hierarchical path name.
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virtual const char *pathName(const Instance *instance) const;
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bool pathNameLess(const Instance *inst1,
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@ -544,6 +547,12 @@ public:
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const char *name) = 0;
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virtual void setIsLeaf(Cell *cell,
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bool is_leaf) = 0;
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virtual void setAttribute(Cell *cell,
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const char *key,
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const char *value) = 0;
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virtual void setAttribute(Instance *instance,
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const char *key,
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const char *value) = 0;
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virtual Port *makePort(Cell *cell,
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const char *name) = 0;
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virtual Port *makeBusPort(Cell *cell,
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@ -45,6 +45,7 @@ public:
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const PatternMatch *pattern) const override;
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const char *name(const Cell *cell) const override;
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const char *getAttribute(const Cell *cell, const char* key) const override;
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ObjectId id(const Cell *cell) const override;
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Library *library(const Cell *cell) const override;
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LibertyCell *libertyCell(Cell *cell) const override;
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@ -80,6 +81,7 @@ public:
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bool hasMembers(const Port *port) const override;
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ObjectId id(const Instance *instance) const override;
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const char *getAttribute(const Instance *inst, const char* key) const override;
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Instance *topInstance() const override;
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Cell *cell(const Instance *instance) const override;
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Instance *parent(const Instance *instance) const override;
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@ -140,6 +140,7 @@ ConcreteCell::~ConcreteCell()
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if (filename_)
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stringDelete(filename_);
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ports_.deleteContents();
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attribute_map_.deleteArrayContents();
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}
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void
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@ -268,6 +269,18 @@ ConcreteCell::setIsLeaf(bool is_leaf)
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is_leaf_ = is_leaf;
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}
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void
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ConcreteCell::setAttribute(const char* key, const char* value)
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{
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attribute_map_.insert(key, stringCopy(value));
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}
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const char *
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ConcreteCell::getAttribute(const char* key) const
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{
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return attribute_map_.findKey(key);
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}
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ConcretePort *
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ConcreteCell::findPort(const char *name) const
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{
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@ -557,6 +557,15 @@ ConcreteNetwork::setIsLeaf(Cell *cell,
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ccell->setIsLeaf(is_leaf);
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}
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void
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ConcreteNetwork::setAttribute(Cell *cell,
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const char *key,
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const char *value)
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{
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ConcreteCell *ccell = reinterpret_cast<ConcreteCell*>(cell);
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ccell->setAttribute(key, value);
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}
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Library *
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ConcreteNetwork::library(const Cell *cell) const
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{
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@ -597,6 +606,13 @@ ConcreteNetwork::filename(const Cell *cell)
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return ccell->filename();
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}
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const char *
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ConcreteNetwork::getAttribute(const Cell *cell, const char *key) const
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{
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const ConcreteCell *ccell = reinterpret_cast<const ConcreteCell*>(cell);
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return ccell->getAttribute(key);
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}
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Port *
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ConcreteNetwork::findPort(const Cell *cell,
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const char *name) const
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@ -921,6 +937,13 @@ ConcreteNetwork::id(const Instance *instance) const
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return inst->id();
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}
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const char *
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ConcreteNetwork::getAttribute(const Instance *inst, const char *key) const
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{
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const ConcreteInstance *cinst = reinterpret_cast<const ConcreteInstance*>(inst);
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return cinst->getAttribute(key);
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}
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Cell *
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ConcreteNetwork::cell(const Instance *instance) const
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{
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@ -1325,6 +1348,15 @@ ConcreteNetwork::connect(Instance *inst,
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return connect(inst, reinterpret_cast<Port*>(port), net);
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}
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void
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ConcreteNetwork::setAttribute(Instance *inst,
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const char *key,
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const char *value)
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{
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ConcreteInstance *cinst = reinterpret_cast<ConcreteInstance*>(inst);
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cinst->setAttribute(key, value);
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}
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Pin *
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ConcreteNetwork::connect(Instance *inst,
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Port *port,
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@ -1564,6 +1596,7 @@ ConcreteInstance::~ConcreteInstance()
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stringDelete(name_);
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delete children_;
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delete nets_;
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attribute_map_.deleteArrayContents();
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}
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Instance *
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@ -1648,6 +1681,18 @@ ConcreteInstance::childIterator() const
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return new ConcreteInstanceChildIterator(children_);
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}
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void
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ConcreteInstance::setAttribute(const char *key, const char *value)
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{
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attribute_map_.insert(key, stringCopy(value));
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}
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const char *
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ConcreteInstance::getAttribute(const char *key) const
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{
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return attribute_map_.findKey(key);
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}
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void
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ConcreteInstance::addChild(ConcreteInstance *child)
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{
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@ -122,6 +122,12 @@ NetworkNameAdapter::id(const Cell *cell) const
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return network_->id(cell);
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}
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const char *
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NetworkNameAdapter::getAttribute(const Cell *cell, const char *key) const
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{
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return network_->getAttribute(cell, key);
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}
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Library *
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NetworkNameAdapter::library(const Cell *cell) const
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{
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@ -327,6 +333,12 @@ NetworkNameAdapter::cell(const Instance *instance) const
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return network_->cell(instance);
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}
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const char *
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NetworkNameAdapter::getAttribute(const Instance *inst, const char *key) const
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{
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return network_->getAttribute(inst, key);
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}
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Instance *
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NetworkNameAdapter::parent(const Instance *instance) const
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{
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@ -4180,11 +4180,13 @@ void finish() { delete self; }
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} // LibertyLibraryIterator methods
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%extend Cell {
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const char *name() { return cmdNetwork()->name(self); }
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Library *library() { return cmdNetwork()->library(self); }
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LibertyCell *liberty_cell() { return cmdNetwork()->libertyCell(self); }
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bool is_leaf() { return cmdNetwork()->isLeaf(self); }
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CellPortIterator *
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port_iterator() { return cmdNetwork()->portIterator(self); }
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const char *get_attribute(const char *key) { return cmdNetwork()->getAttribute(self, key); }
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Port *
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find_port(const char *name)
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@ -119,6 +119,7 @@ record_example_tests {
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multi_corner
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power
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power_vcd
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attribute_parsing_test
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}
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record_sta_tests {
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@ -41,7 +41,6 @@ verilogFlushBuffer()
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%option never-interactive
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%x COMMENT
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%x ATTRIBUTE
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%x QSTRING
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SIGN "+"|"-"
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@ -77,21 +76,6 @@ ID_TOKEN {ID_ESCAPED_TOKEN}|{ID_ALPHA_TOKEN}
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}
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}
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"(*" { BEGIN ATTRIBUTE; }
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<ATTRIBUTE>{
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.
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{EOL} { sta::verilog_reader->incrLine(); }
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"*)" { BEGIN INITIAL; }
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<<EOF>> {
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VerilogParse_error("unterminated attribute");
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BEGIN(INITIAL);
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yyterminate();
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}
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}
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{SIGN}?{UNSIGNED_NUMBER}?"'"[bB][01_xz]+ {
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VerilogParse_lval.constant = sta::stringCopy(VerilogLex_text);
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return CONSTANT;
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@ -121,6 +105,8 @@ ID_TOKEN {ID_ESCAPED_TOKEN}|{ID_ALPHA_TOKEN}
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return ((int) VerilogLex_text[0]);
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}
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"(*" { return ATTRIBUTE_OPEN; }
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"*)" { return ATTRIBUTE_CLOSED; }
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assign { return ASSIGN; }
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endmodule { return ENDMODULE; }
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inout { return INOUT; }
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@ -17,6 +17,8 @@
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// along with this program. If not, see <https://www.gnu.org/licenses/>.
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#include <cstdlib>
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#include <string>
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#include <iostream>
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#include "PortDirection.hh"
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#include "verilog/VerilogReaderPvt.hh"
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@ -33,6 +35,7 @@ int VerilogLex_lex();
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int ival;
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const char *string;
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const char *constant;
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const char *attribute_spec_value;
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sta::VerilogModule *module;
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sta::VerilogStmt *stmt;
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sta::VerilogStmtSeq *stmt_seq;
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@ -44,10 +47,15 @@ int VerilogLex_lex();
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sta::VerilogNet *net;
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sta::VerilogNetBitSelect *net_bit;
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sta::VerilogNetSeq *nets;
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sta::VerilogAttributeEntry *attribute_entry;
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sta::VerilogAttributeEntrySeq *attribute_seq;
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sta::VerilogAttributeStmt *attribute_stmt;
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sta::VerilogAttributeStmtSeq *attribute_stmt_seq;
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}
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%token INT CONSTANT ID STRING MODULE ENDMODULE ASSIGN PARAMETER DEFPARAM
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%token WIRE WAND WOR TRI INPUT OUTPUT INOUT SUPPLY1 SUPPLY0 REG
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%token ATTRIBUTE_OPEN ATTRIBUTE_CLOSED
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%left '-' '+'
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%left '*' '/'
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@ -55,8 +63,10 @@ int VerilogLex_lex();
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%type <string> ID STRING
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%type <ival> WIRE WAND WOR TRI INPUT OUTPUT INOUT SUPPLY1 SUPPLY0
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%type <ival> ATTRIBUTE_OPEN ATTRIBUTE_CLOSED
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%type <ival> INT parameter_exprs parameter_expr module_begin
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%type <constant> CONSTANT
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%type <attribute_spec_value> attr_spec_value
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%type <port_type> dcl_type port_dcl_type
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%type <stmt> stmt declaration instance parameter parameter_dcls parameter_dcl
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%type <stmt> defparam param_values param_value port_dcl
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@ -69,6 +79,10 @@ int VerilogLex_lex();
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%type <net> inst_named_pin net_named net_expr_concat
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%type <nets> port_list port_refs inst_ordered_pins
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%type <nets> inst_named_pins net_exprs inst_pins
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%type <attribute_entry> attr_spec
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%type <attribute_seq> attr_specs
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%type <attribute_stmt> attribute_instance
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%type <attribute_stmt_seq> attribute_instance_seq
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%start file
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@ -92,14 +106,14 @@ module_begin:
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;
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module:
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module_begin ID ';' stmts ENDMODULE
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{ sta::verilog_reader->makeModule($2, new sta::VerilogNetSeq,$4,$1);}
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| module_begin ID '(' ')' ';' stmts ENDMODULE
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{ sta::verilog_reader->makeModule($2, new sta::VerilogNetSeq,$6,$1);}
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| module_begin ID '(' port_list ')' ';' stmts ENDMODULE
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{ sta::verilog_reader->makeModule($2, $4, $7, $1); }
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| module_begin ID '(' port_dcls ')' ';' stmts ENDMODULE
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{ sta::verilog_reader->makeModule($2, $4, $7, $1); }
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attribute_instance_seq module_begin ID ';' stmts ENDMODULE
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{ sta::verilog_reader->makeModule($3, new sta::VerilogNetSeq, $5, $1, $2);}
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| attribute_instance_seq module_begin ID '(' ')' ';' stmts ENDMODULE
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{ sta::verilog_reader->makeModule($3, new sta::VerilogNetSeq, $7, $1, $2);}
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| attribute_instance_seq module_begin ID '(' port_list ')' ';' stmts ENDMODULE
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{ sta::verilog_reader->makeModule($3, $5, $8, $1, $2); }
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| attribute_instance_seq module_begin ID '(' port_dcls ')' ';' stmts ENDMODULE
|
||||
{ sta::verilog_reader->makeModule($3, $5, $8, $1, $2); }
|
||||
;
|
||||
|
||||
port_list:
|
||||
|
|
@ -157,11 +171,12 @@ port_dcls:
|
|||
;
|
||||
|
||||
port_dcl:
|
||||
port_dcl_type { $<ival>$ = sta::verilog_reader->line(); } dcl_arg
|
||||
{ $$ = sta::verilog_reader->makeDcl($1, $3, $<ival>2); }
|
||||
| port_dcl_type { $<ival>$ = sta::verilog_reader->line(); }
|
||||
'[' INT ':' INT ']' dcl_arg
|
||||
{ $$ = sta::verilog_reader->makeDclBus($1, $4, $6, $8, $<ival>2); }
|
||||
attribute_instance_seq port_dcl_type
|
||||
{ $<ival>$ = sta::verilog_reader->line(); } dcl_arg
|
||||
{ $$ = sta::verilog_reader->makeDcl($2, $4, $1, $<ival>3); }
|
||||
| attribute_instance_seq port_dcl_type
|
||||
{ $<ival>$ = sta::verilog_reader->line(); } '[' INT ':' INT ']' dcl_arg
|
||||
{ $$ = sta::verilog_reader->makeDclBus($2, $5, $7, $9, $1, $<ival>3); }
|
||||
;
|
||||
|
||||
port_dcl_type:
|
||||
|
|
@ -282,11 +297,11 @@ param_value:
|
|||
;
|
||||
|
||||
declaration:
|
||||
dcl_type { $<ival>$ = sta::verilog_reader->line(); } dcl_args ';'
|
||||
{ $$ = sta::verilog_reader->makeDcl($1, $3, $<ival>2); }
|
||||
| dcl_type { $<ival>$ = sta::verilog_reader->line(); }
|
||||
attribute_instance_seq dcl_type { $<ival>$ = sta::verilog_reader->line(); } dcl_args ';'
|
||||
{ $$ = sta::verilog_reader->makeDcl($2, $4, $1, $<ival>3); }
|
||||
| attribute_instance_seq dcl_type { $<ival>$ = sta::verilog_reader->line(); }
|
||||
'[' INT ':' INT ']' dcl_args ';'
|
||||
{ $$ = sta::verilog_reader->makeDclBus($1, $4, $6, $8, $<ival>2); }
|
||||
{ $$ = sta::verilog_reader->makeDclBus($2, $5, $7, $9, $1,$<ival>3); }
|
||||
;
|
||||
|
||||
dcl_type:
|
||||
|
|
@ -344,11 +359,11 @@ net_assign_lhs:
|
|||
;
|
||||
|
||||
instance:
|
||||
ID { $<ival>$ = sta::verilog_reader->line(); } ID '(' inst_pins ')' ';'
|
||||
{ $$ = sta::verilog_reader->makeModuleInst($1, $3, $5, $<ival>2); }
|
||||
| ID { $<ival>$ = sta::verilog_reader->line(); } parameter_values
|
||||
attribute_instance_seq ID { $<ival>$ = sta::verilog_reader->line(); } ID '(' inst_pins ')' ';'
|
||||
{ $$ = sta::verilog_reader->makeModuleInst($2, $4, $6, $1, $<ival>3); }
|
||||
| attribute_instance_seq ID { $<ival>$ = sta::verilog_reader->line(); } parameter_values
|
||||
ID '(' inst_pins ')' ';'
|
||||
{ $$ = sta::verilog_reader->makeModuleInst($1, $4, $6, $<ival>2); }
|
||||
{ $$ = sta::verilog_reader->makeModuleInst($2, $5, $7, $1, $<ival>3); }
|
||||
;
|
||||
|
||||
parameter_values:
|
||||
|
|
@ -467,4 +482,46 @@ net_expr:
|
|||
| net_expr_concat
|
||||
;
|
||||
|
||||
attribute_instance_seq:
|
||||
// empty
|
||||
{ $$ = new sta::VerilogAttributeStmtSeq; }
|
||||
| attribute_instance_seq attribute_instance
|
||||
{ if ($2) $1->push_back($2); }
|
||||
;
|
||||
|
||||
attribute_instance:
|
||||
ATTRIBUTE_OPEN attr_specs ATTRIBUTE_CLOSED
|
||||
{
|
||||
$$ = new sta::VerilogAttributeStmt($2);
|
||||
}
|
||||
;
|
||||
|
||||
attr_specs:
|
||||
attr_spec
|
||||
{
|
||||
$$ = new sta::VerilogAttributeEntrySeq;
|
||||
$$->push_back($1);
|
||||
}
|
||||
| attr_spec ',' attr_spec
|
||||
{ $$->push_back($3); }
|
||||
;
|
||||
|
||||
attr_spec:
|
||||
ID
|
||||
{ $$ = new sta::VerilogAttributeEntry($1, "1");}
|
||||
| ID '=' attr_spec_value
|
||||
{
|
||||
$$ = new sta::VerilogAttributeEntry($1, $3);
|
||||
}
|
||||
;
|
||||
|
||||
attr_spec_value:
|
||||
CONSTANT
|
||||
{$$ = $1;}
|
||||
| STRING
|
||||
{$$ = $1;}
|
||||
| INT
|
||||
{$$ = sta::stringCopy(std::to_string($1).c_str());}
|
||||
;
|
||||
|
||||
%%
|
||||
|
|
|
|||
|
|
@ -26,6 +26,7 @@
|
|||
#include "PortDirection.hh"
|
||||
#include "Network.hh"
|
||||
#include "VerilogNamespace.hh"
|
||||
#include "StringUtil.hh"
|
||||
#include "verilog/VerilogReaderPvt.hh"
|
||||
|
||||
extern int
|
||||
|
|
@ -253,6 +254,7 @@ void
|
|||
VerilogReader::makeModule(const char *module_vname,
|
||||
VerilogNetSeq *ports,
|
||||
VerilogStmtSeq *stmts,
|
||||
VerilogAttributeStmtSeq *attribute_stmts,
|
||||
int line)
|
||||
{
|
||||
string module_name = moduleVerilogToSta(module_vname);
|
||||
|
|
@ -263,10 +265,17 @@ VerilogReader::makeModule(const char *module_vname,
|
|||
module_map_.erase(cell);
|
||||
network_->deleteCell(cell);
|
||||
}
|
||||
VerilogModule *module = new VerilogModule(module_name.c_str(),
|
||||
ports, stmts,
|
||||
filename_, line, this);
|
||||
|
||||
VerilogModule *module = new VerilogModule(module_name.c_str(), ports, stmts,
|
||||
attribute_stmts, filename_, line, this);
|
||||
cell = network_->makeCell(library_, module_name.c_str(), false, filename_);
|
||||
|
||||
for (VerilogAttributeStmt *stmt : *attribute_stmts) {
|
||||
for (VerilogAttributeEntry *entry : *stmt->attribute_sequence()) {
|
||||
network_->setAttribute(cell, entry->key(), entry->value());
|
||||
}
|
||||
}
|
||||
|
||||
module_map_[cell] = module;
|
||||
makeCellPorts(cell, module, ports);
|
||||
module_count_++;
|
||||
|
|
@ -277,6 +286,7 @@ void
|
|||
VerilogReader::makeModule(const char *module_name,
|
||||
VerilogStmtSeq *port_dcls,
|
||||
VerilogStmtSeq *stmts,
|
||||
VerilogAttributeStmtSeq *attribute_stmts,
|
||||
int line)
|
||||
{
|
||||
VerilogNetSeq *ports = new VerilogNetSeq;
|
||||
|
|
@ -293,7 +303,7 @@ VerilogReader::makeModule(const char *module_name,
|
|||
}
|
||||
}
|
||||
delete port_dcls;
|
||||
makeModule(module_name, ports, stmts, line);
|
||||
makeModule(module_name, ports, stmts, attribute_stmts, line);
|
||||
}
|
||||
|
||||
void
|
||||
|
|
@ -392,6 +402,7 @@ VerilogReader::checkModuleDcls(VerilogModule *module,
|
|||
VerilogDcl *
|
||||
VerilogReader::makeDcl(PortDirection *dir,
|
||||
VerilogDclArgSeq *args,
|
||||
VerilogAttributeStmtSeq* attribute_stmts,
|
||||
int line)
|
||||
{
|
||||
if (dir->isInternal()) {
|
||||
|
|
@ -411,24 +422,25 @@ VerilogReader::makeDcl(PortDirection *dir,
|
|||
delete args;
|
||||
if (assign_args) {
|
||||
dcl_count_++;
|
||||
return new VerilogDcl(dir, assign_args, line);
|
||||
return new VerilogDcl(dir, assign_args, attribute_stmts, line);
|
||||
}
|
||||
else
|
||||
return nullptr;
|
||||
}
|
||||
else {
|
||||
dcl_count_++;
|
||||
return new VerilogDcl(dir, args, line);
|
||||
return new VerilogDcl(dir, args, attribute_stmts, line);
|
||||
}
|
||||
}
|
||||
|
||||
VerilogDcl *
|
||||
VerilogReader::makeDcl(PortDirection *dir,
|
||||
VerilogDclArg *arg,
|
||||
VerilogAttributeStmtSeq* attribute_stmts,
|
||||
int line)
|
||||
{
|
||||
dcl_count_++;
|
||||
return new VerilogDcl(dir, arg, line);
|
||||
return new VerilogDcl(dir, arg, attribute_stmts, line);
|
||||
}
|
||||
|
||||
VerilogDclBus *
|
||||
|
|
@ -436,10 +448,12 @@ VerilogReader::makeDclBus(PortDirection *dir,
|
|||
int from_index,
|
||||
int to_index,
|
||||
VerilogDclArg *arg,
|
||||
VerilogAttributeStmtSeq* attribute_stmts,
|
||||
int line)
|
||||
{
|
||||
dcl_bus_count_++;
|
||||
return new VerilogDclBus(dir, from_index, to_index, arg, line);
|
||||
return new VerilogDclBus(dir, from_index, to_index, arg, attribute_stmts,
|
||||
line);
|
||||
}
|
||||
|
||||
VerilogDclBus *
|
||||
|
|
@ -447,10 +461,12 @@ VerilogReader::makeDclBus(PortDirection *dir,
|
|||
int from_index,
|
||||
int to_index,
|
||||
VerilogDclArgSeq *args,
|
||||
VerilogAttributeStmtSeq* attribute_stmts,
|
||||
int line)
|
||||
{
|
||||
dcl_bus_count_++;
|
||||
return new VerilogDclBus(dir, from_index, to_index, args, line);
|
||||
return new VerilogDclBus(dir, from_index, to_index, args, attribute_stmts,
|
||||
line);
|
||||
}
|
||||
|
||||
VerilogDclArg *
|
||||
|
|
@ -531,6 +547,7 @@ VerilogInst *
|
|||
VerilogReader::makeModuleInst(const char *module_vname,
|
||||
const char *inst_vname,
|
||||
VerilogNetSeq *pins,
|
||||
VerilogAttributeStmtSeq* attribute_stmts,
|
||||
const int line)
|
||||
{
|
||||
string module_name = moduleVerilogToSta(module_vname);
|
||||
|
|
@ -571,7 +588,7 @@ VerilogReader::makeModuleInst(const char *module_vname,
|
|||
net_port_ref_scalar_net_count_--;
|
||||
}
|
||||
VerilogInst *inst = new VerilogLibertyInst(liberty_cell, inst_name.c_str(),
|
||||
net_names, line);
|
||||
net_names, attribute_stmts, line);
|
||||
delete pins;
|
||||
if (report_stmt_stats_) {
|
||||
inst_names_ += inst_name.size() + 1;
|
||||
|
|
@ -585,7 +602,9 @@ VerilogReader::makeModuleInst(const char *module_vname,
|
|||
else {
|
||||
VerilogInst *inst = new VerilogModuleInst(module_name.c_str(),
|
||||
inst_name.c_str(),
|
||||
pins, line);
|
||||
pins,
|
||||
attribute_stmts,
|
||||
line);
|
||||
if (report_stmt_stats_) {
|
||||
inst_module_names_ += module_name.size() + 1;
|
||||
inst_names_ += inst_name.size() + 1;
|
||||
|
|
@ -819,6 +838,7 @@ VerilogReader::netVerilogName(const char *net_name)
|
|||
VerilogModule::VerilogModule(const char *name,
|
||||
VerilogNetSeq *ports,
|
||||
VerilogStmtSeq *stmts,
|
||||
VerilogAttributeStmtSeq *attribute_stmts,
|
||||
const char *filename,
|
||||
int line,
|
||||
VerilogReader *reader) :
|
||||
|
|
@ -826,7 +846,8 @@ VerilogModule::VerilogModule(const char *name,
|
|||
name_(stringCopy(name)),
|
||||
filename_(filename),
|
||||
ports_(ports),
|
||||
stmts_(stmts)
|
||||
stmts_(stmts),
|
||||
attribute_stmts_(attribute_stmts)
|
||||
{
|
||||
parseStmts(reader);
|
||||
}
|
||||
|
|
@ -837,6 +858,8 @@ VerilogModule::~VerilogModule()
|
|||
delete ports_;
|
||||
stmts_->deleteContents();
|
||||
delete stmts_;
|
||||
attribute_stmts_->deleteContents();
|
||||
delete attribute_stmts_;
|
||||
stringDelete(name_);
|
||||
}
|
||||
|
||||
|
|
@ -936,15 +959,19 @@ VerilogStmt::VerilogStmt(int line) :
|
|||
}
|
||||
|
||||
VerilogInst::VerilogInst(const char *inst_name,
|
||||
VerilogAttributeStmtSeq* attribute_stmts,
|
||||
const int line) :
|
||||
VerilogStmt(line),
|
||||
inst_name_(stringCopy(inst_name))
|
||||
inst_name_(stringCopy(inst_name)),
|
||||
attribute_stmts_(attribute_stmts)
|
||||
{
|
||||
}
|
||||
|
||||
VerilogInst::~VerilogInst()
|
||||
{
|
||||
stringDelete(inst_name_);
|
||||
attribute_stmts_->deleteContents();
|
||||
delete attribute_stmts_;
|
||||
}
|
||||
|
||||
void
|
||||
|
|
@ -957,8 +984,9 @@ VerilogInst::setInstanceName(const char *inst_name)
|
|||
VerilogModuleInst::VerilogModuleInst(const char *module_name,
|
||||
const char *inst_name,
|
||||
VerilogNetSeq *pins,
|
||||
VerilogAttributeStmtSeq* attribute_stmts,
|
||||
int line) :
|
||||
VerilogInst(inst_name, line),
|
||||
VerilogInst(inst_name, attribute_stmts, line),
|
||||
module_name_(stringCopy(module_name)),
|
||||
pins_(pins)
|
||||
{
|
||||
|
|
@ -992,8 +1020,9 @@ VerilogModuleInst::namedPins()
|
|||
VerilogLibertyInst::VerilogLibertyInst(LibertyCell *cell,
|
||||
const char *inst_name,
|
||||
const char **net_names,
|
||||
VerilogAttributeStmtSeq* attribute_stmts,
|
||||
const int line) :
|
||||
VerilogInst(inst_name, line),
|
||||
VerilogInst(inst_name, attribute_stmts, line),
|
||||
cell_(cell),
|
||||
net_names_(net_names)
|
||||
{
|
||||
|
|
@ -1013,27 +1042,33 @@ VerilogLibertyInst::~VerilogLibertyInst()
|
|||
|
||||
VerilogDcl::VerilogDcl(PortDirection *dir,
|
||||
VerilogDclArgSeq *args,
|
||||
VerilogAttributeStmtSeq* attribute_stmts,
|
||||
int line) :
|
||||
VerilogStmt(line),
|
||||
dir_(dir),
|
||||
args_(args)
|
||||
args_(args),
|
||||
attribute_stmts_(attribute_stmts)
|
||||
{
|
||||
}
|
||||
|
||||
VerilogDcl::VerilogDcl(PortDirection *dir,
|
||||
VerilogDclArg *arg,
|
||||
VerilogAttributeStmtSeq* attribute_stmts,
|
||||
int line) :
|
||||
VerilogStmt(line),
|
||||
dir_(dir)
|
||||
{
|
||||
args_ = new VerilogDclArgSeq;
|
||||
args_->push_back(arg);
|
||||
attribute_stmts_ = attribute_stmts;
|
||||
}
|
||||
|
||||
VerilogDcl::~VerilogDcl()
|
||||
{
|
||||
args_->deleteContents();
|
||||
delete args_;
|
||||
attribute_stmts_->deleteContents();
|
||||
delete attribute_stmts_;
|
||||
}
|
||||
|
||||
void
|
||||
|
|
@ -1052,8 +1087,9 @@ VerilogDclBus::VerilogDclBus(PortDirection *dir,
|
|||
int from_index,
|
||||
int to_index,
|
||||
VerilogDclArgSeq *args,
|
||||
VerilogAttributeStmtSeq* attribute_stmts,
|
||||
int line) :
|
||||
VerilogDcl(dir, args, line),
|
||||
VerilogDcl(dir, args, attribute_stmts, line),
|
||||
from_index_(from_index),
|
||||
to_index_(to_index)
|
||||
{
|
||||
|
|
@ -1063,8 +1099,9 @@ VerilogDclBus::VerilogDclBus(PortDirection *dir,
|
|||
int from_index,
|
||||
int to_index,
|
||||
VerilogDclArg *arg,
|
||||
VerilogAttributeStmtSeq* attribute_stmts,
|
||||
int line) :
|
||||
VerilogDcl(dir, arg, line),
|
||||
VerilogDcl(dir, arg, attribute_stmts, line),
|
||||
from_index_(from_index),
|
||||
to_index_(to_index)
|
||||
{
|
||||
|
|
@ -1702,6 +1739,51 @@ VerilogNetPortRefPart::name() const
|
|||
return name_;
|
||||
}
|
||||
|
||||
VerilogAttributeEntry::VerilogAttributeEntry(const char *key,
|
||||
const char * value) :
|
||||
key_(key),
|
||||
value_(value)
|
||||
{
|
||||
}
|
||||
|
||||
VerilogAttributeEntry::~VerilogAttributeEntry()
|
||||
{
|
||||
stringDelete(key_);
|
||||
stringDelete(value_);
|
||||
}
|
||||
|
||||
|
||||
const char *
|
||||
VerilogAttributeEntry::key()
|
||||
{
|
||||
return key_;
|
||||
}
|
||||
|
||||
const char *
|
||||
VerilogAttributeEntry::value()
|
||||
{
|
||||
return value_;
|
||||
}
|
||||
|
||||
VerilogAttributeStmt::VerilogAttributeStmt(
|
||||
VerilogAttributeEntrySeq* attribute_sequence):
|
||||
attribute_sequence_(attribute_sequence)
|
||||
{
|
||||
}
|
||||
|
||||
VerilogAttributeStmt::~VerilogAttributeStmt()
|
||||
{
|
||||
attribute_sequence_->deleteContents();
|
||||
delete attribute_sequence_;
|
||||
}
|
||||
|
||||
VerilogAttributeEntrySeq*
|
||||
VerilogAttributeStmt::attribute_sequence()
|
||||
{
|
||||
return attribute_sequence_;
|
||||
}
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Link verilog network
|
||||
|
|
@ -1859,6 +1941,13 @@ VerilogReader::makeModuleInstNetwork(VerilogModuleInst *mod_inst,
|
|||
cell = network_->cell(lib_cell);
|
||||
Instance *inst = network_->makeInstance(cell, mod_inst->instanceName(),
|
||||
parent);
|
||||
VerilogAttributeStmtSeq *attribute_stmts = mod_inst->attribute_stmts();
|
||||
for (VerilogAttributeStmt *stmt : *attribute_stmts) {
|
||||
for (VerilogAttributeEntry *entry : *stmt->attribute_sequence()) {
|
||||
network_->setAttribute(inst, entry->key(), entry->value());
|
||||
}
|
||||
}
|
||||
|
||||
if (lib_cell) {
|
||||
// Make all pins so timing arcs are built.
|
||||
LibertyCellPortBitIterator port_iter(lib_cell);
|
||||
|
|
@ -2044,6 +2133,12 @@ VerilogReader::makeLibertyInst(VerilogLibertyInst *lib_inst,
|
|||
Cell *cell = reinterpret_cast<Cell*>(lib_cell);
|
||||
Instance *inst = network_->makeInstance(cell, lib_inst->instanceName(),
|
||||
parent);
|
||||
VerilogAttributeStmtSeq *attribute_stmts = lib_inst->attribute_stmts();
|
||||
for (VerilogAttributeStmt *stmt : *attribute_stmts) {
|
||||
for (VerilogAttributeEntry *entry : *stmt->attribute_sequence()) {
|
||||
network_->setAttribute(inst, entry->key(), entry->value());
|
||||
}
|
||||
}
|
||||
const char **net_names = lib_inst->netNames();
|
||||
LibertyCellPortBitIterator port_iter(lib_cell);
|
||||
while (port_iter.hasNext()) {
|
||||
|
|
@ -2205,7 +2300,7 @@ VerilogBindingTbl::find(const char *name, NetworkReader *network)
|
|||
}
|
||||
|
||||
void
|
||||
VerilogBindingTbl::bind(const char *name,
|
||||
VerilogBindingTbl::bind(const char *name,
|
||||
Net *net)
|
||||
{
|
||||
map_[name] = net;
|
||||
|
|
|
|||
|
|
@ -37,6 +37,8 @@ using std::set;
|
|||
|
||||
class Debug;
|
||||
class Report;
|
||||
class VerilogAttributeEntry;
|
||||
class VerilogAttributeStmt;
|
||||
class VerilogReader;
|
||||
class VerilogStmt;
|
||||
class VerilogNet;
|
||||
|
|
@ -60,6 +62,8 @@ class VerilogNetPortRef;
|
|||
class VerilogError;
|
||||
class LibertyCell;
|
||||
|
||||
typedef Vector<VerilogAttributeStmt*> VerilogAttributeStmtSeq;
|
||||
typedef Vector<VerilogAttributeEntry*> VerilogAttributeEntrySeq;
|
||||
typedef Vector<VerilogNet*> VerilogNetSeq;
|
||||
typedef Vector<VerilogStmt*> VerilogStmtSeq;
|
||||
typedef Map<const char*, VerilogDcl*, CharPtrLess> VerilogDclMap;
|
||||
|
|
@ -89,16 +93,20 @@ public:
|
|||
void makeModule(const char *module_name,
|
||||
VerilogNetSeq *ports,
|
||||
VerilogStmtSeq *stmts,
|
||||
VerilogAttributeStmtSeq *attribute_stmts,
|
||||
int line);
|
||||
void makeModule(const char *module_name,
|
||||
VerilogStmtSeq *port_dcls,
|
||||
VerilogStmtSeq *stmts,
|
||||
VerilogAttributeStmtSeq *attribute_stmts,
|
||||
int line);
|
||||
VerilogDcl *makeDcl(PortDirection *dir,
|
||||
VerilogDclArgSeq *args,
|
||||
VerilogAttributeStmtSeq* attribute_stmts,
|
||||
int line);
|
||||
VerilogDcl *makeDcl(PortDirection *dir,
|
||||
VerilogDclArg *arg,
|
||||
VerilogAttributeStmtSeq* attribute_stmts,
|
||||
int line);
|
||||
VerilogDclArg *makeDclArg(const char *net_name);
|
||||
VerilogDclArg*makeDclArg(VerilogAssign *assign);
|
||||
|
|
@ -106,15 +114,18 @@ public:
|
|||
int from_index,
|
||||
int to_index,
|
||||
VerilogDclArg *arg,
|
||||
VerilogAttributeStmtSeq* attribute_stmts,
|
||||
int line);
|
||||
VerilogDclBus *makeDclBus(PortDirection *dir,
|
||||
int from_index,
|
||||
int to_index,
|
||||
VerilogDclArgSeq *args,
|
||||
VerilogAttributeStmtSeq* attribute_stmts,
|
||||
int line);
|
||||
VerilogInst *makeModuleInst(const char *module_name,
|
||||
const char *inst_name,
|
||||
VerilogNetSeq *pins,
|
||||
VerilogAttributeStmtSeq* attribute_stmts,
|
||||
const int line);
|
||||
VerilogAssign *makeAssign(VerilogNet *lhs,
|
||||
VerilogNet *rhs,
|
||||
|
|
@ -328,12 +339,14 @@ public:
|
|||
VerilogModule(const char *name,
|
||||
VerilogNetSeq *ports,
|
||||
VerilogStmtSeq *stmts,
|
||||
VerilogAttributeStmtSeq *attribute_stmts,
|
||||
const char *filename,
|
||||
int line,
|
||||
VerilogReader *reader);
|
||||
virtual ~VerilogModule();
|
||||
const char *name() { return name_; }
|
||||
const char *filename() { return filename_; }
|
||||
VerilogAttributeStmtSeq *attribute_stmts() { return attribute_stmts_; }
|
||||
VerilogNetSeq *ports() { return ports_; }
|
||||
VerilogDcl *declaration(const char *net_name);
|
||||
VerilogStmtSeq *stmts() { return stmts_; }
|
||||
|
|
@ -352,6 +365,7 @@ private:
|
|||
VerilogNetSeq *ports_;
|
||||
VerilogStmtSeq *stmts_;
|
||||
VerilogDclMap dcl_map_;
|
||||
VerilogAttributeStmtSeq *attribute_stmts_;
|
||||
};
|
||||
|
||||
class VerilogDcl : public VerilogStmt
|
||||
|
|
@ -359,9 +373,11 @@ class VerilogDcl : public VerilogStmt
|
|||
public:
|
||||
VerilogDcl(PortDirection *dir,
|
||||
VerilogDclArgSeq *args,
|
||||
VerilogAttributeStmtSeq *attribute_stmts,
|
||||
int line);
|
||||
VerilogDcl(PortDirection *dir,
|
||||
VerilogDclArg *arg,
|
||||
VerilogAttributeStmtSeq *attribute_stmts,
|
||||
int line);
|
||||
virtual ~VerilogDcl();
|
||||
const char *portName();
|
||||
|
|
@ -376,6 +392,7 @@ public:
|
|||
private:
|
||||
PortDirection *dir_;
|
||||
VerilogDclArgSeq *args_;
|
||||
VerilogAttributeStmtSeq *attribute_stmts_;
|
||||
};
|
||||
|
||||
class VerilogDclBus : public VerilogDcl
|
||||
|
|
@ -385,11 +402,13 @@ public:
|
|||
int from_index,
|
||||
int to_index,
|
||||
VerilogDclArgSeq *args,
|
||||
VerilogAttributeStmtSeq* attribute_stmts,
|
||||
int line);
|
||||
VerilogDclBus(PortDirection *dir,
|
||||
int from_index,
|
||||
int to_index,
|
||||
VerilogDclArg *arg,
|
||||
VerilogAttributeStmtSeq* attribute_stmts,
|
||||
int line);
|
||||
virtual bool isBus() const { return true; }
|
||||
int fromIndex() const { return from_index_; }
|
||||
|
|
@ -437,14 +456,17 @@ class VerilogInst : public VerilogStmt
|
|||
{
|
||||
public:
|
||||
VerilogInst(const char *inst_name,
|
||||
VerilogAttributeStmtSeq* attribute_stmts,
|
||||
const int line);
|
||||
virtual ~VerilogInst();
|
||||
virtual bool isInstance() const { return true; }
|
||||
const char *instanceName() const { return inst_name_; }
|
||||
VerilogAttributeStmtSeq *attribute_stmts() const { return attribute_stmts_; }
|
||||
void setInstanceName(const char *inst_name);
|
||||
|
||||
private:
|
||||
const char *inst_name_;
|
||||
VerilogAttributeStmtSeq* attribute_stmts_;
|
||||
};
|
||||
|
||||
class VerilogModuleInst : public VerilogInst
|
||||
|
|
@ -453,6 +475,7 @@ public:
|
|||
VerilogModuleInst(const char *module_name,
|
||||
const char *inst_name,
|
||||
VerilogNetSeq *pins,
|
||||
VerilogAttributeStmtSeq* attribute_stmts,
|
||||
const int line);
|
||||
virtual ~VerilogModuleInst();
|
||||
virtual bool isModuleInst() const { return true; }
|
||||
|
|
@ -475,6 +498,7 @@ public:
|
|||
VerilogLibertyInst(LibertyCell *cell,
|
||||
const char *inst_name,
|
||||
const char **net_names,
|
||||
VerilogAttributeStmtSeq* attribute_stmts,
|
||||
const int line);
|
||||
virtual ~VerilogLibertyInst();
|
||||
virtual bool isLibertyInst() const { return true; }
|
||||
|
|
@ -691,4 +715,29 @@ class VerilogNetNameIterator : public Iterator<const char*>
|
|||
{
|
||||
};
|
||||
|
||||
class VerilogAttributeStmt
|
||||
{
|
||||
public:
|
||||
VerilogAttributeStmt(VerilogAttributeEntrySeq *attribute_sequence);
|
||||
VerilogAttributeEntrySeq *attribute_sequence();
|
||||
virtual ~VerilogAttributeStmt();
|
||||
|
||||
private:
|
||||
VerilogAttributeEntrySeq *attribute_sequence_;
|
||||
};
|
||||
|
||||
class VerilogAttributeEntry
|
||||
{
|
||||
public:
|
||||
VerilogAttributeEntry(const char *key, const char *value);
|
||||
virtual const char *key();
|
||||
virtual const char *value();
|
||||
virtual ~VerilogAttributeEntry();
|
||||
|
||||
private:
|
||||
const char *key_;
|
||||
const char *value_;
|
||||
|
||||
};
|
||||
|
||||
} // namespace
|
||||
|
|
|
|||
Loading…
Reference in New Issue