prima delay calc

Signed-off-by: James Cherry <[email protected]>

test/prima3.ok

@@ -0,0 +1,51 @@
+Warning: asap7_simple.lib.gz line 71510, when attribute inside table model.
+Warning: asap7_simple.lib.gz line 71986, when attribute inside table model.
+Warning: asap7_simple.lib.gz line 72462, when attribute inside table model.
+Warning: asap7_simple.lib.gz line 72938, when attribute inside table model.
+Warning: asap7_simple.lib.gz line 73414, when attribute inside table model.
+Warning: asap7_simple.lib.gz line 74830, when attribute inside table model.
+Warning: asap7_simple.lib.gz line 71029, timing group from output port.
+Warning: asap7_simple.lib.gz line 71505, timing group from output port.
+Warning: asap7_simple.lib.gz line 71981, timing group from output port.
+Warning: asap7_simple.lib.gz line 72457, timing group from output port.
+Warning: asap7_simple.lib.gz line 72933, timing group from output port.
+Warning: asap7_simple.lib.gz line 73409, timing group from output port.
+Warning: asap7_simple.lib.gz line 73885, timing group from output port.
+Warning: asap7_simple.lib.gz line 82276, when attribute inside table model.
+Warning: asap7_simple.lib.gz line 83692, when attribute inside table model.
+Warning: asap7_simple.lib.gz line 81795, timing group from output port.
+Warning: asap7_simple.lib.gz line 82271, timing group from output port.
+Warning: asap7_simple.lib.gz line 82747, timing group from output port.
+Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
+Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
+Path Group: clk
+Path Type: max
+
+   Slew   Delay    Time   Description
+----------------------------------------------------------------
+   0.00    0.00    0.00   clock clk (rise edge)
+           0.00    0.00   clock source latency
+  10.00    0.00    0.00 ^ clk2 (in)
+  48.15   12.04   12.04 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
+  38.97   90.82  102.86 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
+  59.28   16.50  119.36 ^ u1/A (BUFx2_ASAP7_75t_R)
+  70.25   51.69  171.05 ^ u1/Y (BUFx2_ASAP7_75t_R)
+  83.74   18.32  189.37 ^ u2/B (AND2x2_ASAP7_75t_R)
+  72.19   60.76  250.13 ^ u2/Y (AND2x2_ASAP7_75t_R)
+  85.61   18.34  268.46 ^ r3/D (DFFHQx4_ASAP7_75t_R)
+                 268.46   data arrival time
+
+   0.00  500.00  500.00   clock clk (rise edge)
+           0.00  500.00   clock source latency
+  10.00    0.00  500.00 ^ clk3 (in)
+  47.52   11.84  511.84 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
+           0.00  511.84   clock reconvergence pessimism
+         -14.89  496.95   library setup time
+                 496.95   data required time
+----------------------------------------------------------------
+                 496.95   data required time
+                -268.46   data arrival time
+----------------------------------------------------------------
+                 228.48   slack (MET)
+
+

test/prima3.tcl

@@ -0,0 +1,13 @@
+# prima reg1 asap7
+read_liberty asap7_invbuf.lib.gz
+read_liberty asap7_seq.lib.gz
+read_liberty asap7_simple.lib.gz
+read_verilog reg1_asap7.v
+link_design top
+create_clock -name clk -period 500 {clk1 clk2 clk3}
+set_input_delay -clock clk 1 {in1 in2}
+set_input_transition 10 {in1 in2 clk1 clk2 clk3}
+set_propagated_clock {clk1 clk2 clk3}
+read_spef reg1_asap7.spef
+sta::set_delay_calculator prima
+report_checks -fields {input_pins slew} -format full_clock

test/reg1_asap7.spef

@@ -0,0 +1,135 @@
+*SPEF "IEEE 1481-1998"
+*DESIGN "reg1"
+*DATE "Fri Nov 20 13:23:00 2002"
+*VENDOR "Parallax Software, Inc"
+*PROGRAM "Handjob"
+*VERSION "1.0.1c"
+*DESIGN_FLOW "MISSING_NETS"
+*DIVIDER /
+*DELIMITER :
+*BUS_DELIMITER [ ]
+*T_UNIT 1.0 PS
+*C_UNIT 1.0 FF
+*R_UNIT 1.0 KOHM
+*L_UNIT 1.0 UH
+
+*POWER_NETS VDD
+*GROUND_NETS VSS
+
+*PORTS
+in1 I
+in2 I
+clk1 I
+clk2 I
+clk3 I
+out O
+
+*D_NET in1 13.4
+*CONN
+*P in1 I
+*I r1:D I *L .0036
+*CAP
+1 in1 6.7
+2 r1:D 6.7
+*RES
+3 in1 r1:D 2.42
+*END
+
+*D_NET in2 13.4
+*CONN
+*P in2 I
+*I r2:D I *L .0036
+*CAP
+1 in2 6.7
+2 r2:D 6.7
+*RES
+3 in2 r2:D 2.42
+*END
+
+*D_NET clk1 13.4
+*CONN
+*P clk1 I
+*I r1:CLK I *L .0036
+*CAP
+1 clk1 6.7
+2 r1:CLK 6.7
+*RES
+3 clk1 r1:CLK 2.42
+*END
+
+*D_NET clk2 13.4
+*CONN
+*P clk2 I
+*I r2:CLK I *L .0036
+*CAP
+1 clk2 6.7
+2 r2:CLK 6.7
+*RES
+3 clk2 r2:CLK 2.42
+*END
+
+*D_NET clk3 13.4
+*CONN
+*P clk3 I
+*I r3:CLK I *L .0036
+*CAP
+1 clk3 6.7
+2 r3:CLK 6.7
+*RES
+3 clk3 r3:CLK 2.42
+*END
+
+*D_NET r1q 13.4
+*CONN
+*I r1:Q O
+*I u2:A I *L .0086
+*CAP
+1 r1:Q 6.7
+2 u2:A 6.7
+*RES
+3 r1:Q u2:A 2.42
+*END
+
+*D_NET r2q 13.4
+*CONN
+*I r2:Q O
+*I u1:A I *L .0086
+*CAP
+1 r2:Q 6.7
+2 u1:A 6.7
+*RES
+3 r2:Q u1:A 2.42
+*END
+
+*D_NET u1z 13.4
+*CONN
+*I u1:Y O
+*I u2:B I *L .0086
+*CAP
+1 u1:Y 6.7
+2 u2:B 6.7
+*RES
+3 u1:Y u2:B 2.42
+*END
+
+*D_NET u2z 13.4
+*CONN
+*I u2:Y O
+*I r3:D I *L .0086
+*CAP
+1 u2:Y 6.7
+2 r3:D 6.7
+*RES
+3 u2:Y r3:D 2.42
+*END
+
+*D_NET out 13.4
+*CONN
+*I r3:Q O
+*P out O
+*CAP
+1 r3:Q 6.7
+2 out 6.7
+*RES
+3 r3:Q out 2.42
+*END

test/reg1_asap7.v

@@ -0,0 +1,11 @@
+module top (in1, in2, clk1, clk2, clk3, out);
+  input in1, in2, clk1, clk2, clk3;
+  output out;
+  wire r1q, r2q, u1z, u2z;
+
+  DFFHQx4_ASAP7_75t_R r1 (.D(in1), .CLK(clk1), .Q(r1q));
+  DFFHQx4_ASAP7_75t_R r2 (.D(in2), .CLK(clk2), .Q(r2q));
+  BUFx2_ASAP7_75t_R u1 (.A(r2q), .Y(u1z));
+  AND2x2_ASAP7_75t_R u2 (.A(r1q), .B(u1z), .Y(u2z));
+  DFFHQx4_ASAP7_75t_R r3 (.D(u2z), .CLK(clk3), .Q(out));
+endmodule // top

test/regression_vars.tcl

@@ -123,6 +123,7 @@ record_example_tests {
 
 record_sta_tests {
   ccs_sim1
+  prima3
   verilog_attribute
 }