no crpr for ideal clks
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2627ed3812
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3d4b0cf1a3
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@ -165,6 +165,8 @@ CheckCrpr::checkCrpr1(const Path *src_path,
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const MinMax *src_clk_min_max =
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const MinMax *src_clk_min_max =
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src_clk_path ? src_clk_path->minMax(this) : src_path->minMax(this);
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src_clk_path ? src_clk_path->minMax(this) : src_path->minMax(this);
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if (crprPossible(src_clk, tgt_clk)
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if (crprPossible(src_clk, tgt_clk)
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&& src_clk_info->isPropagated()
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&& tgt_clk_info->isPropagated()
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// Note that crpr clk min/max is NOT the same as the path min max.
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// Note that crpr clk min/max is NOT the same as the path min max.
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// For path from latches that are borrowing the enable path
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// For path from latches that are borrowing the enable path
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// is from the opposite min/max of the data.
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// is from the opposite min/max of the data.
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@ -372,9 +374,12 @@ CheckCrpr::outputDelayCrpr1(const Path *src_path,
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{
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{
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crpr = 0.0;
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crpr = 0.0;
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crpr_pin = nullptr;
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crpr_pin = nullptr;
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ClkInfo *src_clk_info = src_path->tag(this)->clkInfo();
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Clock *tgt_clk = tgt_clk_edge->clock();
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Clock *tgt_clk = tgt_clk_edge->clock();
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Clock *src_clk = src_path->clock(this);
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Clock *src_clk = src_path->clock(this);
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if (tgt_clk->isGenerated()
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if (src_clk_info->isPropagated()
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&& tgt_clk->isGenerated()
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&& tgt_clk->isPropagated()
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&& crprPossible(src_clk, tgt_clk)) {
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&& crprPossible(src_clk, tgt_clk)) {
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PathVertex tgt_genclk_path;
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PathVertex tgt_genclk_path;
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portClkPath(tgt_clk_edge, tgt_clk_edge->clock()->defaultPin(), tgt_path_ap,
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portClkPath(tgt_clk_edge, tgt_clk_edge->clock()->defaultPin(), tgt_path_ap,
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@ -393,7 +398,7 @@ CheckCrpr::crprPossible(Clock *clk1,
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return clk1 && clk2
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return clk1 && clk2
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&& !clk1->isVirtual()
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&& !clk1->isVirtual()
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&& !clk2->isVirtual()
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&& !clk2->isVirtual()
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// Generated clock can have crpr in the source path.
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// Generated clocks can have crpr in the source path.
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&& (clk1 == clk2
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&& (clk1 == clk2
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|| clk1->isGenerated()
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|| clk1->isGenerated()
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|| clk2->isGenerated()
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|| clk2->isGenerated()
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