power reg activity prop
This commit is contained in:
James Cherry
parent
e0dad2ea19
commit
325e284441
187
search/Power.cc
187
search/Power.cc
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@ -103,6 +103,12 @@ Power::pinActivity(const Pin *pin)
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return activity_map_[pin];
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}
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bool
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Power::hasPinActivity(const Pin *pin)
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{
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return activity_map_.hasKey(pin);
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}
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void
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Power::setPinActivity(const Pin *pin,
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float activity,
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@ -218,10 +224,16 @@ class PropActivityVisitor : public VertexVisitor, StaState
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public:
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PropActivityVisitor(Power *power,
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BfsFwdIterator *bfs);
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~PropActivityVisitor();
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virtual VertexVisitor *copy();
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virtual void visit(Vertex *vertex);
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void init();
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bool foundRegWithoutActivity() const;
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InstanceSet *stealVisitedRegs();
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private:
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InstanceSet *visited_regs_;
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bool found_reg_without_activity_;
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Power *power_;
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BfsFwdIterator *bfs_;
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};
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@ -229,17 +241,88 @@ private:
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PropActivityVisitor::PropActivityVisitor(Power *power,
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BfsFwdIterator *bfs) :
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StaState(power),
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visited_regs_(nullptr),
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power_(power),
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bfs_(bfs)
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{
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}
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PropActivityVisitor::~PropActivityVisitor()
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{
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delete visited_regs_;
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}
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VertexVisitor *
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PropActivityVisitor::copy()
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{
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return new PropActivityVisitor(power_, bfs_);
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}
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void
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PropActivityVisitor::init()
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{
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visited_regs_ = new InstanceSet;
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found_reg_without_activity_ = false;
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}
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InstanceSet *
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PropActivityVisitor::stealVisitedRegs()
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{
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InstanceSet *visited_regs = visited_regs_;
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visited_regs_ = nullptr;
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return visited_regs;
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}
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bool
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PropActivityVisitor::foundRegWithoutActivity() const
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{
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return found_reg_without_activity_;
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}
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void
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PropActivityVisitor::visit(Vertex *vertex)
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{
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auto pin = vertex->pin();
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debugPrint1(debug_, "power_activity", 3, "visit %s\n",
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vertex->name(network_));
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bool input_without_activity = false;
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if (network_->isLoad(pin)) {
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VertexInEdgeIterator edge_iter(vertex, graph_);
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if (edge_iter.hasNext()) {
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Edge *edge = edge_iter.next();
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if (edge->isWire()) {
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Vertex *from_vertex = edge->from(graph_);
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const Pin *from_pin = from_vertex->pin();
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PwrActivity &from_activity = power_->pinActivity(from_pin);
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PwrActivity to_activity(from_activity.activity(),
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from_activity.duty(),
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PwrActivityOrigin::propagated);
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if (!power_->hasPinActivity(pin))
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input_without_activity = true;
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power_->setPinActivity(pin, to_activity);
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}
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}
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Instance *inst = network_->instance(pin);
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auto cell = network_->libertyCell(inst);
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if (cell && cell->hasSequentials()) {
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debugPrint1(debug_, "power_activity", 3, "pending reg %s\n",
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network_->pathName(inst));
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visited_regs_->insert(inst);
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found_reg_without_activity_ = input_without_activity;
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}
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}
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if (network_->isDriver(pin)) {
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LibertyPort *port = network_->libertyPort(pin);
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if (port) {
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FuncExpr *func = port->function();
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Instance *inst = network_->instance(pin);
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PwrActivity activity = power_->evalActivity(func, inst);
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power_->setPinActivity(pin, activity);
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}
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}
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bfs_->enqueueAdjacentVertices(vertex);
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}
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PwrActivity
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Power::evalActivity(FuncExpr *expr,
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const Instance *inst)
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@ -292,39 +375,6 @@ Power::evalActivity(FuncExpr *expr,
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return PwrActivity();
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}
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void
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PropActivityVisitor::visit(Vertex *vertex)
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{
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auto pin = vertex->pin();
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debugPrint1(debug_, "power", 3, "activity %s\n",
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vertex->name(network_));
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if (network_->isLoad(pin)) {
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VertexInEdgeIterator edge_iter(vertex, graph_);
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if (edge_iter.hasNext()) {
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Edge *edge = edge_iter.next();
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if (edge->isWire()) {
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Vertex *from_vertex = edge->from(graph_);
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const Pin *from_pin = from_vertex->pin();
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PwrActivity &from_activity = power_->pinActivity(from_pin);
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PwrActivity to_activity(from_activity.activity(),
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from_activity.duty(),
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PwrActivityOrigin::propagated);
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power_->setPinActivity(pin, to_activity);
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}
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}
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}
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if (network_->isDriver(pin)) {
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LibertyPort *port = network_->libertyPort(pin);
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if (port) {
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FuncExpr *func = port->function();
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Instance *inst = network_->instance(pin);
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PwrActivity activity = power_->evalActivity(func, inst);
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power_->setPinActivity(pin, activity);
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}
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}
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bfs_->enqueueAdjacentVertices(vertex);
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}
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////////////////////////////////////////////////////////////////
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void
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@ -342,10 +392,19 @@ Power::ensureActivities()
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BfsFwdIterator bfs(BfsIndex::other, &activity_srch_pred, this);
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seedActivities(bfs);
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PropActivityVisitor visitor(this, &bfs);
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visitor.init();
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bfs.visit(levelize_->maxLevel(), &visitor);
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// Propagate activiities across register D->Q.
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seedRegOutputActivities(bfs);
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bfs.visit(levelize_->maxLevel(), &visitor);
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while (visitor.foundRegWithoutActivity()) {
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InstanceSet *regs = visitor.stealVisitedRegs();
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InstanceSet::Iterator reg_iter(regs);
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while (reg_iter.hasNext()) {
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auto reg = reg_iter.next();
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// Propagate activiities across register D->Q.
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seedRegOutputActivities(reg, bfs);
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}
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visitor.init();
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bfs.visit(levelize_->maxLevel(), &visitor);
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}
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activities_valid_ = true;
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}
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}
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@ -357,54 +416,54 @@ Power::seedActivities(BfsFwdIterator &bfs)
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for (auto vertex : levelize_->roots()) {
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const Pin *pin = vertex->pin();
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// Clock activities are baked in.
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if (!sdc_->isVertexPinClock(pin)) {
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if (!sdc_->isVertexPinClock(pin)
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&& network_->direction(pin) != PortDirection::internal()) {
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PwrActivity &activity = pinActivity(pin);
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PwrActivityOrigin origin = activity.origin();
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// Default inputs without explicit activities to the input default.
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if (origin != PwrActivityOrigin::user)
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setPinActivity(pin, input_activity_);
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Vertex *vertex = graph_->pinDrvrVertex(pin);
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debugPrint1(debug_, "power_activity", 3, "seed %s\n",
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vertex->name(network_));
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bfs.enqueueAdjacentVertices(vertex);
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}
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}
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}
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void
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Power::seedRegOutputActivities(BfsFwdIterator &bfs)
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Power::seedRegOutputActivities(const Instance *inst,
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BfsFwdIterator &bfs)
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{
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LeafInstanceIterator *leaf_iter = network_->leafInstanceIterator();
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while (leaf_iter->hasNext()) {
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auto inst = leaf_iter->next();
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auto cell = network_->libertyCell(inst);
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if (cell) {
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LibertyCellSequentialIterator seq_iter(cell);
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while (seq_iter.hasNext()) {
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Sequential *seq = seq_iter.next();
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seedRegOutputActivities(inst, seq, seq->output(), false);
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seedRegOutputActivities(inst, seq, seq->outputInv(), true);
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// Enqueue register output pins with functions that reference
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// the sequential internal pins (IQ, IQN).
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InstancePinIterator *pin_iter = network_->pinIterator(inst);
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while (pin_iter->hasNext()) {
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auto pin = pin_iter->next();
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auto port = network_->libertyPort(pin);
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auto func = port->function();
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if (func) {
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Vertex *vertex = graph_->pinDrvrVertex(pin);
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if (func->port() == seq->output()
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|| func->port() == seq->outputInv())
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bfs.enqueue(vertex);
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}
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auto cell = network_->libertyCell(inst);
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LibertyCellSequentialIterator seq_iter(cell);
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while (seq_iter.hasNext()) {
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Sequential *seq = seq_iter.next();
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seedRegOutputActivities(inst, seq, seq->output(), false);
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seedRegOutputActivities(inst, seq, seq->outputInv(), true);
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// Enqueue register output pins with functions that reference
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// the sequential internal pins (IQ, IQN).
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InstancePinIterator *pin_iter = network_->pinIterator(inst);
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while (pin_iter->hasNext()) {
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auto pin = pin_iter->next();
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auto port = network_->libertyPort(pin);
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auto func = port->function();
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if (func) {
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Vertex *vertex = graph_->pinDrvrVertex(pin);
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if (func->port() == seq->output()
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|| func->port() == seq->outputInv()) {
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debugPrint1(debug_, "power_activity", 3, "enqueue reg output %s\n",
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vertex->name(network_));
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bfs.enqueue(vertex);
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}
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delete pin_iter;
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}
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}
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delete pin_iter;
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}
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delete leaf_iter;
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}
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void
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Power::seedRegOutputActivities(Instance *reg,
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Power::seedRegOutputActivities(const Instance *reg,
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Sequential *seq,
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LibertyPort *output,
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bool invert)
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@ -88,6 +88,7 @@ public:
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float activity,
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float duty);
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PwrActivity &pinActivity(const Pin *pin);
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bool hasPinActivity(const Pin *pin);
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void setPinActivity(const Pin *pin,
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float activity,
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float duty,
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@ -133,11 +134,12 @@ protected:
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const LibertyPort *port,
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const DcalcAnalysisPt *dcalc_ap);
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void seedActivities(BfsFwdIterator &bfs);
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void seedRegOutputActivities(BfsFwdIterator &bfs);
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void seedRegOutputActivities(Instance *reg,
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void seedRegOutputActivities(const Instance *reg,
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Sequential *seq,
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LibertyPort *output,
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bool invert);
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void seedRegOutputActivities(const Instance *inst,
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BfsFwdIterator &bfs);
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PwrActivity evalActivity(FuncExpr *expr,
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const Instance *inst);
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23
tcl/Cmds.tcl
23
tcl/Cmds.tcl
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@ -22,6 +22,29 @@
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namespace eval sta {
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proc report_clock1 { clk } {
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global sta_report_default_digits
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if { [$clk waveform_valid] } {
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set digits $sta_report_default_digits
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puts -nonewline [format "%-20s" [get_name $clk]]
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puts -nonewline [format "%10s" [format_time [$clk period] $digits]]
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puts -nonewline " "
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set waveform [$clk waveform]
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if { $waveform == {} } {
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puts -nonewline " "
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} else {
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foreach edge $waveform {
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puts -nonewline [format "%10s" [format_time $edge $digits]]
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}
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}
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if {[$clk is_generated]} {
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puts -nonewline " (generated)"
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}
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puts ""
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}
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}
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proc_redirect read_parasitics {
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variable native
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23
tcl/Sta.tcl
23
tcl/Sta.tcl
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@ -944,29 +944,6 @@ proc_redirect report_clock_properties {
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}
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}
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proc report_clock1 { clk } {
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global sta_report_default_digits
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if { [$clk waveform_valid] } {
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set digits $sta_report_default_digits
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puts -nonewline [format "%-20s" [$clk name]]
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puts -nonewline [format "%10s" [format_time [$clk period] $digits]]
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puts -nonewline " "
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set waveform [$clk waveform]
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if { $waveform == {} } {
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puts -nonewline " "
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} else {
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foreach edge $waveform {
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puts -nonewline [format "%10s" [format_time $edge $digits]]
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}
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}
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if {[$clk is_generated]} {
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puts -nonewline " (generated)"
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}
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puts ""
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}
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}
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################################################################
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define_sta_cmd_args "report_object_full_names" {[-verbose] objects}
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