mirror of
https://github.com/The-OpenROAD-Project/OpenSTA.git
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DelayCalc reorg
commit 410ed56c2c2d0d7afb0e84d0c65d5ff75234e9e3 Author: James Cherry <[email protected]> Date: Sun Nov 19 08:44:13 2023 -0700 ArcDelayCalcBase -> DelayCalcBase Signed-off-by: James Cherry <[email protected]> commit 1fdfebe2838c47f6c1866c8a10b14df6439506e0 Author: James Cherry <[email protected]> Date: Sun Nov 19 08:25:36 2023 -0700 LumpedCapDelayCalc::inputPortDelay Signed-off-by: James Cherry <[email protected]> commit 3a5e1d01aaff240b2f71d006d620ccd6a70bce6d Author: James Cherry <[email protected]> Date: Fri Nov 17 16:32:32 2023 -0700 gateDelayInit cleanup Signed-off-by: James Cherry <[email protected]> commit d0133319126ae4a488a7b31679fbf6507c7f6266 Author: James Cherry <[email protected]> Date: Fri Nov 17 15:36:12 2023 -0700 mv RCDelayCalc to ArcDelayCalcBase Signed-off-by: James Cherry <[email protected]> commit fd028e6ba5e092243a84685eb1756a8e4e4bad76 Author: James Cherry <[email protected]> Date: Fri Nov 17 14:32:53 2023 -0700 ArcDelayCalcBase Signed-off-by: James Cherry <[email protected]> commit 0ce9cf4c766f7419b998b40aed5af14df97249f1 Author: James Cherry <[email protected]> Date: Fri Nov 17 10:57:41 2023 -0700 ParallelArcDelayCalc -> ParallelDelayCalc Signed-off-by: James Cherry <[email protected]> commit 7fa7db6b252f1450fa5b546f5d33d8cb8a94d4bb Author: James Cherry <[email protected]> Date: Fri Nov 17 08:45:01 2023 -0700 parallelGateDelay args Signed-off-by: James Cherry <[email protected]> commit 6b85756774ce049c0f5f123f6d60ebbcd62cdd2b Author: James Cherry <[email protected]> Date: Thu Nov 16 19:55:20 2023 -0700 TimingModel cell_ Signed-off-by: James Cherry <[email protected]> commit e536d6b0ca0d01e2ad8bd609ad20f9a02497d8f5 Author: James Cherry <[email protected]> Date: Thu Nov 16 18:07:11 2023 -0700 TimingModel cell_ Signed-off-by: James Cherry <[email protected]> commit d2d622da4206e06d176e4ae741334fde8df35007 Author: James Cherry <[email protected]> Date: Thu Nov 16 17:21:15 2023 -0700 rm drvr_cell from arc dcalc funcs Signed-off-by: James Cherry <[email protected]> commit 522961e8f58bc1a0f0530a0a5218086280a2bcb0 Author: James Cherry <[email protected]> Date: Thu Nov 16 16:24:34 2023 -0700 tr -> rf Signed-off-by: James Cherry <[email protected]> commit 29aa0ed40345611b9e3a898342ecc17f6355396f Author: James Cherry <[email protected]> Date: Thu Nov 16 13:17:44 2023 -0700 GraphDelayCalc Signed-off-by: James Cherry <[email protected]> commit 934d9f19c52c62925b23ae9b457f14d25e818f1a Author: James Cherry <[email protected]> Date: Thu Nov 16 12:52:55 2023 -0700 ParallelArcDelayCalc Signed-off-by: James Cherry <[email protected]> commit d5687d9482ad0f572b017f0ef806ba8e6ff8b6fa Author: James Cherry <[email protected]> Date: Thu Nov 16 12:16:05 2023 -0700 ParallelArcDelayCalc pvt Signed-off-by: James Cherry <[email protected]> commit 0de501e5bf2329364b572d1360c18d5aedf3b841 Author: James Cherry <[email protected]> Date: Thu Nov 16 10:46:22 2023 -0700 ParallelArcDelayCalc::findMultiDrvrGateDelay Signed-off-by: James Cherry <[email protected]> commit d7457b9e335ed5fa583798e0512914aab6524fcc Author: James Cherry <[email protected]> Date: Thu Nov 16 10:19:01 2023 -0700 mv multi_drvr_slew_factor_ to ParallelArcDelayCalc Signed-off-by: James Cherry <[email protected]> commit afec4daa2ab6dd61a2450f1ac8a8cad1ef015a29 Author: James Cherry <[email protected]> Date: Thu Nov 16 08:02:40 2023 -0700 MultiDrvrNet::net_caps vector Signed-off-by: James Cherry <[email protected]> commit b450b3a35616ffc8d85610158a91c5d9483b6958 Author: James Cherry <[email protected]> Date: Thu Nov 16 07:46:43 2023 -0700 sic Signed-off-by: James Cherry <[email protected]> commit 65767403b3b2ab4e6f7552625accf9aa4766628a Author: James Cherry <[email protected]> Date: Tue Nov 14 17:49:22 2023 -0700 Sta::connectedCap simplify Signed-off-by: James Cherry <[email protected]> commit 85bdb8f3362413e7b05f49447a0383140cbb924f Author: James Cherry <[email protected]> Date: Tue Nov 14 16:43:38 2023 -0700 ParallelArcDelayCalc Signed-off-by: James Cherry <[email protected]> commit 4feea3ba2277d53697b644d79832e309ce98058a Author: James Cherry <[email protected]> Date: Tue Nov 14 15:10:18 2023 -0700 mv parallel dcalc to arc delay calc Signed-off-by: James Cherry <[email protected]> commit 915ed28a2c05acce6569c7933366ef94da8bfaeb Author: James Cherry <[email protected]> Date: Mon Nov 13 17:47:14 2023 -0700 rm MultiDrvrNet::delays_valid_ Signed-off-by: James Cherry <[email protected]> commit 2384eb4e5bdca1410c4bf5e23f35bfb49f013e74 Author: James Cherry <[email protected]> Date: Mon Nov 13 16:02:57 2023 -0700 mkae MultiDrvrNets on the fly Signed-off-by: James Cherry <[email protected]> Signed-off-by: James Cherry <[email protected]>
This commit is contained in:
+33
-19
@@ -17,6 +17,7 @@
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#pragma once
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#include <string>
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#include <vector>
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#include "MinMax.hh"
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#include "LibertyClass.hh"
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@@ -28,22 +29,26 @@
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namespace sta {
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using std::string;
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using std::vector;
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class Parasitic;
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class DcalcAnalysisPt;
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class MultiDrvrNet;
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// Delay calculator class hierarchy.
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// ArcDelayCalc
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// UnitDelayCalc
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// LumpedCapDelayCalc
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// RCDelayCalc
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// SlewDegradeDelayCalc
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// DmpCeffDelayCalc
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// DmpCeffElmoreDelayCalc
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// DmpCeffTwoPoleDelayCalc
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// ArnoldiDelayCalc
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// DelayCalcBase
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// ParallelDelayCalc
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// LumpedCapDelayCalc
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// SlewDegradeDelayCalc
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// DmpCeffDelayCalc
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// DmpCeffElmoreDelayCalc
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// DmpCeffTwoPoleDelayCalc
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// ArnoldiDelayCalc
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// Abstract class to interface to a delay calculator primitive.
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// Abstract class for the graph delay calculator traversal to interface
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// to a delay calculator primitive.
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class ArcDelayCalc : public StaState
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{
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public:
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@@ -66,8 +71,7 @@ public:
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const DcalcAnalysisPt *dcalc_ap) = 0;
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// Find the delay and slew for arc driving drvr_pin.
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virtual void gateDelay(const LibertyCell *drvr_cell,
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const TimingArc *arc,
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virtual void gateDelay(const TimingArc *arc,
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const Slew &in_slew,
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// Pass in load_cap or drvr_parasitic.
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float load_cap,
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@@ -78,16 +82,29 @@ public:
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// Return values.
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ArcDelay &gate_delay,
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Slew &drvr_slew) = 0;
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// Find gate delays and slews for parallel gates.
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virtual void findParallelGateDelays(const MultiDrvrNet *multi_drvr,
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GraphDelayCalc *dcalc) = 0;
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// Retrieve the delay and slew for one parallel gate.
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virtual void parallelGateDelay(const Pin *drvr_pin,
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const TimingArc *arc,
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const Slew &from_slew,
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float load_cap,
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const Parasitic *drvr_parasitic,
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float related_out_cap,
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const Pvt *pvt,
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const DcalcAnalysisPt *dcalc_ap,
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// Return values.
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ArcDelay &gate_delay,
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Slew &gate_slew) = 0;
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// Find the wire delay and load slew of a load pin.
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// Called after inputPortDelay or gateDelay.
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virtual void loadDelay(const Pin *load_pin,
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// Return values.
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ArcDelay &wire_delay,
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Slew &load_slew) = 0;
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virtual void setMultiDrvrSlewFactor(float factor) = 0;
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// Ceff for parasitics with pi models.
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virtual float ceff(const LibertyCell *drvr_cell,
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const TimingArc *arc,
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virtual float ceff(const TimingArc *arc,
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const Slew &in_slew,
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float load_cap,
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const Parasitic *drvr_parasitic,
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@@ -97,8 +114,7 @@ public:
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// Find the delay for a timing check arc given the arc's
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// from/clock, to/data slews and related output pin parasitic.
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virtual void checkDelay(const LibertyCell *drvr_cell,
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const TimingArc *arc,
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virtual void checkDelay(const TimingArc *arc,
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const Slew &from_slew,
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const Slew &to_slew,
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float related_out_cap,
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@@ -107,8 +123,7 @@ public:
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// Return values.
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ArcDelay &margin) = 0;
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// Report delay and slew calculation.
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virtual string reportGateDelay(const LibertyCell *drvr_cell,
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const TimingArc *arc,
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virtual string reportGateDelay(const TimingArc *arc,
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const Slew &in_slew,
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// Pass in load_cap or drvr_parasitic.
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float load_cap,
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@@ -118,8 +133,7 @@ public:
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const DcalcAnalysisPt *dcalc_ap,
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int digits) = 0;
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// Report timing check delay calculation.
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virtual string reportCheckDelay(const LibertyCell *cell,
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const TimingArc *arc,
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virtual string reportCheckDelay(const TimingArc *arc,
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const Slew &from_slew,
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const char *from_slew_annotation,
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const Slew &to_slew,
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@@ -157,11 +157,11 @@ public:
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DcalcAPIndex ap_index,
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const ArcDelay &delay);
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// Is timing arc delay annotated.
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bool arcDelayAnnotated(Edge *edge,
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TimingArc *arc,
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bool arcDelayAnnotated(const Edge *edge,
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const TimingArc *arc,
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DcalcAPIndex ap_index) const;
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void setArcDelayAnnotated(Edge *edge,
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TimingArc *arc,
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const TimingArc *arc,
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DcalcAPIndex ap_index,
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bool annotated);
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bool wireDelayAnnotated(Edge *edge,
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@@ -539,7 +539,6 @@ class VertexSet : public Set<Vertex*, VertexIdLess>
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{
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public:
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VertexSet(Graph *&graph);
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VertexSet(const VertexSet &set);
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};
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} // namespace
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@@ -16,6 +16,8 @@
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#pragma once
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#include <vector>
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#include "Map.hh"
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#include "NetworkClass.hh"
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#include "GraphClass.hh"
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@@ -26,9 +28,12 @@
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namespace sta {
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using std::vector;
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class DelayCalcObserver;
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class MultiDrvrNet;
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class FindVertexDelays;
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class NetCaps;
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typedef Map<const Vertex*, MultiDrvrNet*> MultiDrvrNetMap;
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@@ -55,8 +60,8 @@ public:
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// Find and annotate drvr_vertex gate and load delays/slews.
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virtual void findDelays(Vertex *drvr_vertex);
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// Returned string is owned by the caller.
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virtual string reportDelayCalc(Edge *edge,
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TimingArc *arc,
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virtual string reportDelayCalc(const Edge *edge,
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const TimingArc *arc,
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const Corner *corner,
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const MinMax *min_max,
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int digits);
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@@ -85,6 +90,11 @@ public:
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const Parasitic *drvr_parasitic,
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const RiseFall *rf,
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const DcalcAnalysisPt *dcalc_ap) const;
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float loadCap(const Pin *drvr_pin,
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const Parasitic *drvr_parasitic,
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const RiseFall *rf,
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const DcalcAnalysisPt *dcalc_ap,
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const MultiDrvrNet *multi_drvr) const;
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virtual void netCaps(const Pin *drvr_pin,
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const RiseFall *rf,
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const DcalcAnalysisPt *dcalc_ap,
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@@ -115,10 +125,13 @@ public:
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float &min_period,
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bool &exists);
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Slew edgeFromSlew(const Vertex *from_vertex,
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const RiseFall *from_rf,
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const Edge *edge,
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const DcalcAnalysisPt *dcalc_ap);
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protected:
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void seedInvalidDelays();
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void ensureMultiDrvrNetsFound();
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void makeMultiDrvrNet(PinSet &drvr_pins);
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void initSlew(Vertex *vertex);
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void seedRootSlew(Vertex *vertex,
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ArcDelayCalc *arc_delay_calc);
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@@ -150,23 +163,23 @@ protected:
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const LibertyPort *to_port);
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int findPortIndex(const LibertyCell *cell,
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const LibertyPort *port);
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void findInputArcDelay(const LibertyCell *drvr_cell,
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const Pin *drvr_pin,
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void findInputArcDelay(const Pin *drvr_pin,
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Vertex *drvr_vertex,
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const TimingArc *arc,
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float from_slew,
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const DcalcAnalysisPt *dcalc_ap);
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bool findDriverDelays(Vertex *drvr_vertex,
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ArcDelayCalc *arc_delay_calc);
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MultiDrvrNet *findMultiDrvrNet(Vertex *drvr_pin);
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MultiDrvrNet *makeMultiDrvrNet(PinSet &drvr_pins);
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bool findDriverDelays1(Vertex *drvr_vertex,
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MultiDrvrNet *multi_drvr,
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ArcDelayCalc *arc_delay_calc);
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void initLoadSlews(Vertex *drvr_vertex);
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bool findDriverEdgeDelays(LibertyCell *drvr_cell,
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Instance *drvr_inst,
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bool findDriverEdgeDelays(const Instance *drvr_inst,
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const Pin *drvr_pin,
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Vertex *drvr_vertex,
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MultiDrvrNet *multi_drvr,
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const MultiDrvrNet *multi_drvr,
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Edge *edge,
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ArcDelayCalc *arc_delay_calc);
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void initWireDelays(Vertex *drvr_vertex);
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@@ -176,17 +189,16 @@ protected:
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ArcDelayCalc *arc_delay_calc,
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bool propagate);
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void enqueueTimingChecksEdges(Vertex *vertex);
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bool findArcDelay(LibertyCell *drvr_cell,
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const Pin *drvr_pin,
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bool findArcDelay(const Pin *drvr_pin,
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Vertex *drvr_vertex,
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MultiDrvrNet *multi_drvr,
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TimingArc *arc,
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Parasitic *drvr_parasitic,
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const TimingArc *arc,
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const Parasitic *drvr_parasitic,
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float related_out_cap,
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Vertex *from_vertex,
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Edge *edge,
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const Pvt *pvt,
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const DcalcAnalysisPt *dcalc_ap,
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const MultiDrvrNet *multi_drvr,
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ArcDelayCalc *arc_delay_calc);
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void annotateLoadDelays(Vertex *drvr_vertex,
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const RiseFall *drvr_rf,
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@@ -197,32 +209,7 @@ protected:
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void findLatchEdgeDelays(Edge *edge);
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void findCheckEdgeDelays(Edge *edge,
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ArcDelayCalc *arc_delay_calc);
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void findMultiDrvrGateDelay(MultiDrvrNet *multi_drvr,
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const RiseFall *drvr_rf,
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const Pvt *pvt,
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const DcalcAnalysisPt *dcalc_ap,
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ArcDelayCalc *arc_delay_calc,
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// Return values.
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ArcDelay ¶llel_delay,
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Slew ¶llel_slew);
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void parallelGateDelay(MultiDrvrNet *multi_drvr,
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LibertyCell *drvr_cell,
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const Pin *drvr_pin,
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TimingArc *arc,
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const Pvt *pvt,
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const DcalcAnalysisPt *dcalc_ap,
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const Slew from_slew,
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Parasitic *drvr_parasitic,
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float related_out_cap,
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ArcDelayCalc *arc_delay_calc,
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// Return values.
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ArcDelay &gate_delay,
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Slew &gate_slew);
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void deleteMultiDrvrNets();
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Slew edgeFromSlew(const Vertex *from_vertex,
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const RiseFall *from_rf,
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const Edge *edge,
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const DcalcAnalysisPt *dcalc_ap);
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Slew checkEdgeClkSlew(const Vertex *from_vertex,
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const RiseFall *from_rf,
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const DcalcAnalysisPt *dcalc_ap);
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@@ -233,11 +220,6 @@ protected:
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// Return values.
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float &pin_cap,
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float &wire_cap) const;
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float loadCap(const Pin *drvr_pin,
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MultiDrvrNet *multi_drvr,
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const Parasitic *drvr_parasitic,
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const RiseFall *rf,
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const DcalcAnalysisPt *dcalc_ap) const;
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// Observer for edge delay changes.
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DelayCalcObserver *observer_;
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@@ -277,4 +259,33 @@ public:
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virtual void checkDelayChangedTo(Vertex *vertex) = 0;
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};
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// Nets with multiple drivers (tristate, bidirect or output).
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// Cache net caps to prevent N^2 net pin walk.
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class MultiDrvrNet
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{
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public:
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MultiDrvrNet(VertexSet *drvrs);
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~MultiDrvrNet();
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const VertexSet *drvrs() const { return drvrs_; }
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VertexSet *drvrs() { return drvrs_; }
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bool parallelGates(const Network *network) const;
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Vertex *dcalcDrvr() const { return dcalc_drvr_; }
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void setDcalcDrvr(Vertex *drvr);
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void netCaps(const RiseFall *rf,
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const DcalcAnalysisPt *dcalc_ap,
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// Return values.
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float &pin_cap,
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float &wire_cap,
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float &fanout,
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bool &has_net_load) const;
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void findCaps(const Sdc *sdc);
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private:
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// Driver that triggers delay calculation for all the drivers on the net.
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Vertex *dcalc_drvr_;
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VertexSet *drvrs_;
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// [drvr_rf->index][dcalc_ap->index]
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vector<NetCaps> net_caps_;
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};
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} // namespace
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@@ -167,16 +167,14 @@ public:
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const LibertyCell *cell,
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const Pvt *pvt) const;
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float scaleFactor(ScaleFactorType type,
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int tr_index,
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int rf_index,
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const LibertyCell *cell,
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const Pvt *pvt) const;
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void setWireSlewDegradationTable(TableModel *model,
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RiseFall *rf);
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TableModel *wireSlewDegradationTable(const RiseFall *rf) const;
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float degradeWireSlew(const LibertyCell *cell,
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const RiseFall *rf,
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const Pvt *pvt,
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float degradeWireSlew(const RiseFall *rf,
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float in_slew,
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float wire_delay) const;
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// Check for supported axis variables.
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@@ -323,9 +321,7 @@ public:
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void addDriverWaveform(DriverWaveform *driver_waveform);
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protected:
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float degradeWireSlew(const LibertyCell *cell,
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const Pvt *pvt,
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const TableModel *model,
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float degradeWireSlew(const TableModel *model,
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float in_slew,
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float wire_delay) const;
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@@ -925,7 +921,7 @@ public:
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RiseFall *rf);
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float scale(ScaleFactorType type,
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ScaleFactorPvt pvt,
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int tr_index);
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int rf_index);
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float scale(ScaleFactorType type,
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ScaleFactorPvt pvt);
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void setScale(ScaleFactorType type,
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+10
-12
@@ -23,9 +23,10 @@ namespace sta {
|
||||
class GateLinearModel : public GateTimingModel
|
||||
{
|
||||
public:
|
||||
GateLinearModel(float intrinsic, float resistance);
|
||||
void gateDelay(const LibertyCell *cell,
|
||||
const Pvt *pvt,
|
||||
GateLinearModel(LibertyCell *cell,
|
||||
float intrinsic,
|
||||
float resistance);
|
||||
void gateDelay(const Pvt *pvt,
|
||||
float in_slew,
|
||||
float load_cap,
|
||||
float related_out_cap,
|
||||
@@ -33,15 +34,13 @@ public:
|
||||
// Return values.
|
||||
ArcDelay &gate_delay,
|
||||
Slew &drvr_slew) const override;
|
||||
string reportGateDelay(const LibertyCell *cell,
|
||||
const Pvt *pvt,
|
||||
string reportGateDelay(const Pvt *pvt,
|
||||
float in_slew,
|
||||
float load_cap,
|
||||
float related_out_cap,
|
||||
bool pocv_enabled,
|
||||
int digits) const override;
|
||||
float driveResistance(const LibertyCell *cell,
|
||||
const Pvt *pvt) const override;
|
||||
float driveResistance(const Pvt *pvt) const override;
|
||||
|
||||
protected:
|
||||
void setIsScaled(bool is_scaled) override;
|
||||
@@ -53,17 +52,16 @@ protected:
|
||||
class CheckLinearModel : public CheckTimingModel
|
||||
{
|
||||
public:
|
||||
explicit CheckLinearModel(float intrinsic);
|
||||
void checkDelay(const LibertyCell *cell,
|
||||
const Pvt *pvt,
|
||||
explicit CheckLinearModel(LibertyCell *cell,
|
||||
float intrinsic);
|
||||
void checkDelay(const Pvt *pvt,
|
||||
float from_slew,
|
||||
float to_slew,
|
||||
float related_out_cap,
|
||||
bool pocv_enabled,
|
||||
// Return values.
|
||||
ArcDelay &margin) const override;
|
||||
string reportCheckDelay(const LibertyCell *cell,
|
||||
const Pvt *pvt,
|
||||
string reportCheckDelay(const Pvt *pvt,
|
||||
float from_slew,
|
||||
const char *from_slew_annotation,
|
||||
float to_slew,
|
||||
|
||||
+2
-1
@@ -827,7 +827,8 @@ public:
|
||||
// Returns nullptr if set_operating_conditions has not been called.
|
||||
OperatingConditions *operatingConditions(const MinMax *min_max);
|
||||
// Instance specific process/voltage/temperature.
|
||||
const Pvt *pvt(Instance *inst, const MinMax *min_max) const;
|
||||
const Pvt *pvt(const Instance *inst,
|
||||
const MinMax *min_max) const;
|
||||
// Pvt may be shared among multiple instances.
|
||||
void setPvt(const Instance *inst,
|
||||
const MinMaxAll *min_max,
|
||||
|
||||
+15
-36
@@ -51,15 +51,15 @@ tableVariableUnit(TableAxisVariable variable,
|
||||
class GateTableModel : public GateTimingModel
|
||||
{
|
||||
public:
|
||||
GateTableModel(TableModel *delay_model,
|
||||
GateTableModel(LibertyCell *cell,
|
||||
TableModel *delay_model,
|
||||
TableModel *delay_sigma_models[EarlyLate::index_count],
|
||||
TableModel *slew_model,
|
||||
TableModel *slew_sigma_models[EarlyLate::index_count],
|
||||
ReceiverModelPtr receiver_model,
|
||||
OutputWaveforms *output_waveforms);
|
||||
virtual ~GateTableModel();
|
||||
void gateDelay(const LibertyCell *cell,
|
||||
const Pvt *pvt,
|
||||
void gateDelay(const Pvt *pvt,
|
||||
float in_slew,
|
||||
float load_cap,
|
||||
float related_out_cap,
|
||||
@@ -67,15 +67,13 @@ public:
|
||||
// Return values.
|
||||
ArcDelay &gate_delay,
|
||||
Slew &drvr_slew) const override;
|
||||
string reportGateDelay(const LibertyCell *cell,
|
||||
const Pvt *pvt,
|
||||
string reportGateDelay(const Pvt *pvt,
|
||||
float in_slew,
|
||||
float load_cap,
|
||||
float related_out_cap,
|
||||
bool pocv_enabled,
|
||||
int digits) const override;
|
||||
float driveResistance(const LibertyCell *cell,
|
||||
const Pvt *pvt) const override;
|
||||
float driveResistance(const Pvt *pvt) const override;
|
||||
|
||||
const TableModel *delayModel() const { return delay_model_; }
|
||||
const TableModel *slewModel() const { return slew_model_; }
|
||||
@@ -86,8 +84,7 @@ public:
|
||||
static bool checkAxes(const TablePtr table);
|
||||
|
||||
protected:
|
||||
void maxCapSlew(const LibertyCell *cell,
|
||||
float in_slew,
|
||||
void maxCapSlew(float in_slew,
|
||||
const Pvt *pvt,
|
||||
float &slew,
|
||||
float &cap) const;
|
||||
@@ -96,16 +93,12 @@ protected:
|
||||
float load_cap,
|
||||
float in_slew,
|
||||
float related_out_cap) const;
|
||||
float findValue(const LibertyLibrary *library,
|
||||
const LibertyCell *cell,
|
||||
const Pvt *pvt,
|
||||
float findValue(const Pvt *pvt,
|
||||
const TableModel *model,
|
||||
float in_slew,
|
||||
float load_cap,
|
||||
float related_out_cap) const;
|
||||
string reportTableLookup(const char *result_name,
|
||||
const LibertyLibrary *library,
|
||||
const LibertyCell *cell,
|
||||
const Pvt *pvt,
|
||||
const TableModel *model,
|
||||
float in_slew,
|
||||
@@ -133,19 +126,18 @@ protected:
|
||||
class CheckTableModel : public CheckTimingModel
|
||||
{
|
||||
public:
|
||||
explicit CheckTableModel(TableModel *model,
|
||||
explicit CheckTableModel(LibertyCell *cell,
|
||||
TableModel *model,
|
||||
TableModel *sigma_models[EarlyLate::index_count]);
|
||||
virtual ~CheckTableModel();
|
||||
void checkDelay(const LibertyCell *cell,
|
||||
const Pvt *pvt,
|
||||
void checkDelay(const Pvt *pvt,
|
||||
float from_slew,
|
||||
float to_slew,
|
||||
float related_out_cap,
|
||||
bool pocv_enabled,
|
||||
// Return values.
|
||||
ArcDelay &margin) const override;
|
||||
string reportCheckDelay(const LibertyCell *cell,
|
||||
const Pvt *pvt,
|
||||
string reportCheckDelay(const Pvt *pvt,
|
||||
float from_slew,
|
||||
const char *from_slew_annotation,
|
||||
float to_slew,
|
||||
@@ -160,9 +152,7 @@ public:
|
||||
|
||||
protected:
|
||||
void setIsScaled(bool is_scaled) override;
|
||||
float findValue(const LibertyLibrary *library,
|
||||
const LibertyCell *cell,
|
||||
const Pvt *pvt,
|
||||
float findValue(const Pvt *pvt,
|
||||
const TableModel *model,
|
||||
float from_slew,
|
||||
float to_slew,
|
||||
@@ -179,8 +169,6 @@ protected:
|
||||
float in_slew,
|
||||
float related_out_cap) const;
|
||||
string reportTableDelay(const char *result_name,
|
||||
const LibertyLibrary *library,
|
||||
const LibertyCell *cell,
|
||||
const Pvt *pvt,
|
||||
const TableModel *model,
|
||||
float from_slew,
|
||||
@@ -217,14 +205,12 @@ public:
|
||||
float value2,
|
||||
float value3) const;
|
||||
// Table interpolated lookup with scale factor.
|
||||
float findValue(const LibertyLibrary *library,
|
||||
const LibertyCell *cell,
|
||||
float findValue(const LibertyCell *cell,
|
||||
const Pvt *pvt,
|
||||
float value1,
|
||||
float value2,
|
||||
float value3) const;
|
||||
string reportValue(const char *result_name,
|
||||
const LibertyLibrary *library,
|
||||
const LibertyCell *cell,
|
||||
const Pvt *pvt,
|
||||
float value1,
|
||||
@@ -237,11 +223,9 @@ public:
|
||||
Report *report) const;
|
||||
|
||||
protected:
|
||||
float scaleFactor(const LibertyLibrary *library,
|
||||
const LibertyCell *cell,
|
||||
float scaleFactor(const LibertyCell *cell,
|
||||
const Pvt *pvt) const;
|
||||
string reportPvtScaleFactor(const LibertyLibrary *library,
|
||||
const LibertyCell *cell,
|
||||
string reportPvtScaleFactor(const LibertyCell *cell,
|
||||
const Pvt *pvt,
|
||||
int digits) const;
|
||||
|
||||
@@ -280,7 +264,6 @@ public:
|
||||
float axis_value2,
|
||||
float axis_value3) const;
|
||||
virtual string reportValue(const char *result_name,
|
||||
const LibertyLibrary *library,
|
||||
const LibertyCell *cell,
|
||||
const Pvt *pvt,
|
||||
float value1,
|
||||
@@ -306,7 +289,6 @@ public:
|
||||
float axis_value2,
|
||||
float axis_value3) const override;
|
||||
string reportValue(const char *result_name,
|
||||
const LibertyLibrary *library,
|
||||
const LibertyCell *cell,
|
||||
const Pvt *pvt,
|
||||
float value1,
|
||||
@@ -342,7 +324,6 @@ public:
|
||||
float value2,
|
||||
float value3) const override;
|
||||
string reportValue(const char *result_name,
|
||||
const LibertyLibrary *library,
|
||||
const LibertyCell *cell,
|
||||
const Pvt *pvt,
|
||||
float value1,
|
||||
@@ -389,7 +370,6 @@ public:
|
||||
float value2,
|
||||
float value3) const override;
|
||||
string reportValue(const char *result_name,
|
||||
const LibertyLibrary *library,
|
||||
const LibertyCell *cell,
|
||||
const Pvt *pvt,
|
||||
float value1,
|
||||
@@ -436,7 +416,6 @@ public:
|
||||
float value2,
|
||||
float value3) const override;
|
||||
string reportValue(const char *result_name,
|
||||
const LibertyLibrary *library,
|
||||
const LibertyCell *cell,
|
||||
const Pvt *pvt,
|
||||
float value1,
|
||||
|
||||
+10
-13
@@ -29,21 +29,21 @@ using std::string;
|
||||
class TimingModel
|
||||
{
|
||||
public:
|
||||
TimingModel(LibertyCell *cell);
|
||||
virtual ~TimingModel() {}
|
||||
|
||||
protected:
|
||||
virtual void setIsScaled(bool is_scaled) = 0;
|
||||
|
||||
friend class LibertyCell;
|
||||
protected:
|
||||
LibertyCell *cell_;
|
||||
};
|
||||
|
||||
// Abstract base class for LinearModel and TableModel.
|
||||
class GateTimingModel : public TimingModel
|
||||
{
|
||||
public:
|
||||
GateTimingModel(LibertyCell *cell);
|
||||
// Gate delay calculation.
|
||||
virtual void gateDelay(const LibertyCell *cell,
|
||||
const Pvt *pvt,
|
||||
virtual void gateDelay(const Pvt *pvt,
|
||||
float in_slew,
|
||||
float load_cap,
|
||||
float related_out_cap,
|
||||
@@ -51,32 +51,29 @@ public:
|
||||
// Return values.
|
||||
ArcDelay &gate_delay,
|
||||
Slew &drvr_slew) const = 0;
|
||||
virtual string reportGateDelay(const LibertyCell *cell,
|
||||
const Pvt *pvt,
|
||||
virtual string reportGateDelay(const Pvt *pvt,
|
||||
float in_slew,
|
||||
float load_cap,
|
||||
float related_out_cap,
|
||||
bool pocv_enabled,
|
||||
int digits) const = 0;
|
||||
virtual float driveResistance(const LibertyCell *cell,
|
||||
const Pvt *pvt) const = 0;
|
||||
virtual float driveResistance(const Pvt *pvt) const = 0;
|
||||
};
|
||||
|
||||
// Abstract base class for timing check timing models.
|
||||
class CheckTimingModel : public TimingModel
|
||||
{
|
||||
public:
|
||||
CheckTimingModel(LibertyCell *cell);
|
||||
// Timing check margin delay calculation.
|
||||
virtual void checkDelay(const LibertyCell *cell,
|
||||
const Pvt *pvt,
|
||||
virtual void checkDelay(const Pvt *pvt,
|
||||
float from_slew,
|
||||
float to_slew,
|
||||
float related_out_cap,
|
||||
bool pocv_enabled,
|
||||
// Return values.
|
||||
ArcDelay &margin) const = 0;
|
||||
virtual string reportCheckDelay(const LibertyCell *cell,
|
||||
const Pvt *pvt,
|
||||
virtual string reportCheckDelay(const Pvt *pvt,
|
||||
float from_slew,
|
||||
const char *from_slew_annotation,
|
||||
float to_slew,
|
||||
|
||||
Reference in New Issue
Block a user