DelayCalc reorg

commit 410ed56c2c2d0d7afb0e84d0c65d5ff75234e9e3
Author: James Cherry <[email protected]>
Date:   Sun Nov 19 08:44:13 2023 -0700

    ArcDelayCalcBase -> DelayCalcBase

    Signed-off-by: James Cherry <[email protected]>

commit 1fdfebe2838c47f6c1866c8a10b14df6439506e0
Author: James Cherry <[email protected]>
Date:   Sun Nov 19 08:25:36 2023 -0700

    LumpedCapDelayCalc::inputPortDelay

    Signed-off-by: James Cherry <[email protected]>

commit 3a5e1d01aaff240b2f71d006d620ccd6a70bce6d
Author: James Cherry <[email protected]>
Date:   Fri Nov 17 16:32:32 2023 -0700

    gateDelayInit cleanup

    Signed-off-by: James Cherry <[email protected]>

commit d0133319126ae4a488a7b31679fbf6507c7f6266
Author: James Cherry <[email protected]>
Date:   Fri Nov 17 15:36:12 2023 -0700

    mv RCDelayCalc to ArcDelayCalcBase

    Signed-off-by: James Cherry <[email protected]>

commit fd028e6ba5e092243a84685eb1756a8e4e4bad76
Author: James Cherry <[email protected]>
Date:   Fri Nov 17 14:32:53 2023 -0700

    ArcDelayCalcBase

    Signed-off-by: James Cherry <[email protected]>

commit 0ce9cf4c766f7419b998b40aed5af14df97249f1
Author: James Cherry <[email protected]>
Date:   Fri Nov 17 10:57:41 2023 -0700

    ParallelArcDelayCalc -> ParallelDelayCalc

    Signed-off-by: James Cherry <[email protected]>

commit 7fa7db6b252f1450fa5b546f5d33d8cb8a94d4bb
Author: James Cherry <[email protected]>
Date:   Fri Nov 17 08:45:01 2023 -0700

    parallelGateDelay args

    Signed-off-by: James Cherry <[email protected]>

commit 6b85756774ce049c0f5f123f6d60ebbcd62cdd2b
Author: James Cherry <[email protected]>
Date:   Thu Nov 16 19:55:20 2023 -0700

    TimingModel cell_

    Signed-off-by: James Cherry <[email protected]>

commit e536d6b0ca0d01e2ad8bd609ad20f9a02497d8f5
Author: James Cherry <[email protected]>
Date:   Thu Nov 16 18:07:11 2023 -0700

    TimingModel cell_

    Signed-off-by: James Cherry <[email protected]>

commit d2d622da4206e06d176e4ae741334fde8df35007
Author: James Cherry <[email protected]>
Date:   Thu Nov 16 17:21:15 2023 -0700

    rm drvr_cell from arc dcalc funcs

    Signed-off-by: James Cherry <[email protected]>

commit 522961e8f58bc1a0f0530a0a5218086280a2bcb0
Author: James Cherry <[email protected]>
Date:   Thu Nov 16 16:24:34 2023 -0700

    tr -> rf

    Signed-off-by: James Cherry <[email protected]>

commit 29aa0ed40345611b9e3a898342ecc17f6355396f
Author: James Cherry <[email protected]>
Date:   Thu Nov 16 13:17:44 2023 -0700

    GraphDelayCalc

    Signed-off-by: James Cherry <[email protected]>

commit 934d9f19c52c62925b23ae9b457f14d25e818f1a
Author: James Cherry <[email protected]>
Date:   Thu Nov 16 12:52:55 2023 -0700

    ParallelArcDelayCalc

    Signed-off-by: James Cherry <[email protected]>

commit d5687d9482ad0f572b017f0ef806ba8e6ff8b6fa
Author: James Cherry <[email protected]>
Date:   Thu Nov 16 12:16:05 2023 -0700

    ParallelArcDelayCalc pvt

    Signed-off-by: James Cherry <[email protected]>

commit 0de501e5bf2329364b572d1360c18d5aedf3b841
Author: James Cherry <[email protected]>
Date:   Thu Nov 16 10:46:22 2023 -0700

    ParallelArcDelayCalc::findMultiDrvrGateDelay

    Signed-off-by: James Cherry <[email protected]>

commit d7457b9e335ed5fa583798e0512914aab6524fcc
Author: James Cherry <[email protected]>
Date:   Thu Nov 16 10:19:01 2023 -0700

    mv multi_drvr_slew_factor_ to ParallelArcDelayCalc

    Signed-off-by: James Cherry <[email protected]>

commit afec4daa2ab6dd61a2450f1ac8a8cad1ef015a29
Author: James Cherry <[email protected]>
Date:   Thu Nov 16 08:02:40 2023 -0700

    MultiDrvrNet::net_caps vector

    Signed-off-by: James Cherry <[email protected]>

commit b450b3a35616ffc8d85610158a91c5d9483b6958
Author: James Cherry <[email protected]>
Date:   Thu Nov 16 07:46:43 2023 -0700

    sic

    Signed-off-by: James Cherry <[email protected]>

commit 65767403b3b2ab4e6f7552625accf9aa4766628a
Author: James Cherry <[email protected]>
Date:   Tue Nov 14 17:49:22 2023 -0700

    Sta::connectedCap simplify

    Signed-off-by: James Cherry <[email protected]>

commit 85bdb8f3362413e7b05f49447a0383140cbb924f
Author: James Cherry <[email protected]>
Date:   Tue Nov 14 16:43:38 2023 -0700

    ParallelArcDelayCalc

    Signed-off-by: James Cherry <[email protected]>

commit 4feea3ba2277d53697b644d79832e309ce98058a
Author: James Cherry <[email protected]>
Date:   Tue Nov 14 15:10:18 2023 -0700

    mv parallel dcalc to arc delay calc

    Signed-off-by: James Cherry <[email protected]>

commit 915ed28a2c05acce6569c7933366ef94da8bfaeb
Author: James Cherry <[email protected]>
Date:   Mon Nov 13 17:47:14 2023 -0700

    rm MultiDrvrNet::delays_valid_

    Signed-off-by: James Cherry <[email protected]>

commit 2384eb4e5bdca1410c4bf5e23f35bfb49f013e74
Author: James Cherry <[email protected]>
Date:   Mon Nov 13 16:02:57 2023 -0700

    mkae MultiDrvrNets on the fly

    Signed-off-by: James Cherry <[email protected]>

Signed-off-by: James Cherry <[email protected]>
This commit is contained in:
James Cherry
2023-11-19 10:04:45 -07:00
parent 19cf68c72a
commit 31369dd750
37 changed files with 1070 additions and 1170 deletions
+33 -19
View File
@@ -17,6 +17,7 @@
#pragma once
#include <string>
#include <vector>
#include "MinMax.hh"
#include "LibertyClass.hh"
@@ -28,22 +29,26 @@
namespace sta {
using std::string;
using std::vector;
class Parasitic;
class DcalcAnalysisPt;
class MultiDrvrNet;
// Delay calculator class hierarchy.
// ArcDelayCalc
// UnitDelayCalc
// LumpedCapDelayCalc
// RCDelayCalc
// SlewDegradeDelayCalc
// DmpCeffDelayCalc
// DmpCeffElmoreDelayCalc
// DmpCeffTwoPoleDelayCalc
// ArnoldiDelayCalc
// DelayCalcBase
// ParallelDelayCalc
// LumpedCapDelayCalc
// SlewDegradeDelayCalc
// DmpCeffDelayCalc
// DmpCeffElmoreDelayCalc
// DmpCeffTwoPoleDelayCalc
// ArnoldiDelayCalc
// Abstract class to interface to a delay calculator primitive.
// Abstract class for the graph delay calculator traversal to interface
// to a delay calculator primitive.
class ArcDelayCalc : public StaState
{
public:
@@ -66,8 +71,7 @@ public:
const DcalcAnalysisPt *dcalc_ap) = 0;
// Find the delay and slew for arc driving drvr_pin.
virtual void gateDelay(const LibertyCell *drvr_cell,
const TimingArc *arc,
virtual void gateDelay(const TimingArc *arc,
const Slew &in_slew,
// Pass in load_cap or drvr_parasitic.
float load_cap,
@@ -78,16 +82,29 @@ public:
// Return values.
ArcDelay &gate_delay,
Slew &drvr_slew) = 0;
// Find gate delays and slews for parallel gates.
virtual void findParallelGateDelays(const MultiDrvrNet *multi_drvr,
GraphDelayCalc *dcalc) = 0;
// Retrieve the delay and slew for one parallel gate.
virtual void parallelGateDelay(const Pin *drvr_pin,
const TimingArc *arc,
const Slew &from_slew,
float load_cap,
const Parasitic *drvr_parasitic,
float related_out_cap,
const Pvt *pvt,
const DcalcAnalysisPt *dcalc_ap,
// Return values.
ArcDelay &gate_delay,
Slew &gate_slew) = 0;
// Find the wire delay and load slew of a load pin.
// Called after inputPortDelay or gateDelay.
virtual void loadDelay(const Pin *load_pin,
// Return values.
ArcDelay &wire_delay,
Slew &load_slew) = 0;
virtual void setMultiDrvrSlewFactor(float factor) = 0;
// Ceff for parasitics with pi models.
virtual float ceff(const LibertyCell *drvr_cell,
const TimingArc *arc,
virtual float ceff(const TimingArc *arc,
const Slew &in_slew,
float load_cap,
const Parasitic *drvr_parasitic,
@@ -97,8 +114,7 @@ public:
// Find the delay for a timing check arc given the arc's
// from/clock, to/data slews and related output pin parasitic.
virtual void checkDelay(const LibertyCell *drvr_cell,
const TimingArc *arc,
virtual void checkDelay(const TimingArc *arc,
const Slew &from_slew,
const Slew &to_slew,
float related_out_cap,
@@ -107,8 +123,7 @@ public:
// Return values.
ArcDelay &margin) = 0;
// Report delay and slew calculation.
virtual string reportGateDelay(const LibertyCell *drvr_cell,
const TimingArc *arc,
virtual string reportGateDelay(const TimingArc *arc,
const Slew &in_slew,
// Pass in load_cap or drvr_parasitic.
float load_cap,
@@ -118,8 +133,7 @@ public:
const DcalcAnalysisPt *dcalc_ap,
int digits) = 0;
// Report timing check delay calculation.
virtual string reportCheckDelay(const LibertyCell *cell,
const TimingArc *arc,
virtual string reportCheckDelay(const TimingArc *arc,
const Slew &from_slew,
const char *from_slew_annotation,
const Slew &to_slew,
+3 -4
View File
@@ -157,11 +157,11 @@ public:
DcalcAPIndex ap_index,
const ArcDelay &delay);
// Is timing arc delay annotated.
bool arcDelayAnnotated(Edge *edge,
TimingArc *arc,
bool arcDelayAnnotated(const Edge *edge,
const TimingArc *arc,
DcalcAPIndex ap_index) const;
void setArcDelayAnnotated(Edge *edge,
TimingArc *arc,
const TimingArc *arc,
DcalcAPIndex ap_index,
bool annotated);
bool wireDelayAnnotated(Edge *edge,
@@ -539,7 +539,6 @@ class VertexSet : public Set<Vertex*, VertexIdLess>
{
public:
VertexSet(Graph *&graph);
VertexSet(const VertexSet &set);
};
} // namespace
+55 -44
View File
@@ -16,6 +16,8 @@
#pragma once
#include <vector>
#include "Map.hh"
#include "NetworkClass.hh"
#include "GraphClass.hh"
@@ -26,9 +28,12 @@
namespace sta {
using std::vector;
class DelayCalcObserver;
class MultiDrvrNet;
class FindVertexDelays;
class NetCaps;
typedef Map<const Vertex*, MultiDrvrNet*> MultiDrvrNetMap;
@@ -55,8 +60,8 @@ public:
// Find and annotate drvr_vertex gate and load delays/slews.
virtual void findDelays(Vertex *drvr_vertex);
// Returned string is owned by the caller.
virtual string reportDelayCalc(Edge *edge,
TimingArc *arc,
virtual string reportDelayCalc(const Edge *edge,
const TimingArc *arc,
const Corner *corner,
const MinMax *min_max,
int digits);
@@ -85,6 +90,11 @@ public:
const Parasitic *drvr_parasitic,
const RiseFall *rf,
const DcalcAnalysisPt *dcalc_ap) const;
float loadCap(const Pin *drvr_pin,
const Parasitic *drvr_parasitic,
const RiseFall *rf,
const DcalcAnalysisPt *dcalc_ap,
const MultiDrvrNet *multi_drvr) const;
virtual void netCaps(const Pin *drvr_pin,
const RiseFall *rf,
const DcalcAnalysisPt *dcalc_ap,
@@ -115,10 +125,13 @@ public:
float &min_period,
bool &exists);
Slew edgeFromSlew(const Vertex *from_vertex,
const RiseFall *from_rf,
const Edge *edge,
const DcalcAnalysisPt *dcalc_ap);
protected:
void seedInvalidDelays();
void ensureMultiDrvrNetsFound();
void makeMultiDrvrNet(PinSet &drvr_pins);
void initSlew(Vertex *vertex);
void seedRootSlew(Vertex *vertex,
ArcDelayCalc *arc_delay_calc);
@@ -150,23 +163,23 @@ protected:
const LibertyPort *to_port);
int findPortIndex(const LibertyCell *cell,
const LibertyPort *port);
void findInputArcDelay(const LibertyCell *drvr_cell,
const Pin *drvr_pin,
void findInputArcDelay(const Pin *drvr_pin,
Vertex *drvr_vertex,
const TimingArc *arc,
float from_slew,
const DcalcAnalysisPt *dcalc_ap);
bool findDriverDelays(Vertex *drvr_vertex,
ArcDelayCalc *arc_delay_calc);
MultiDrvrNet *findMultiDrvrNet(Vertex *drvr_pin);
MultiDrvrNet *makeMultiDrvrNet(PinSet &drvr_pins);
bool findDriverDelays1(Vertex *drvr_vertex,
MultiDrvrNet *multi_drvr,
ArcDelayCalc *arc_delay_calc);
void initLoadSlews(Vertex *drvr_vertex);
bool findDriverEdgeDelays(LibertyCell *drvr_cell,
Instance *drvr_inst,
bool findDriverEdgeDelays(const Instance *drvr_inst,
const Pin *drvr_pin,
Vertex *drvr_vertex,
MultiDrvrNet *multi_drvr,
const MultiDrvrNet *multi_drvr,
Edge *edge,
ArcDelayCalc *arc_delay_calc);
void initWireDelays(Vertex *drvr_vertex);
@@ -176,17 +189,16 @@ protected:
ArcDelayCalc *arc_delay_calc,
bool propagate);
void enqueueTimingChecksEdges(Vertex *vertex);
bool findArcDelay(LibertyCell *drvr_cell,
const Pin *drvr_pin,
bool findArcDelay(const Pin *drvr_pin,
Vertex *drvr_vertex,
MultiDrvrNet *multi_drvr,
TimingArc *arc,
Parasitic *drvr_parasitic,
const TimingArc *arc,
const Parasitic *drvr_parasitic,
float related_out_cap,
Vertex *from_vertex,
Edge *edge,
const Pvt *pvt,
const DcalcAnalysisPt *dcalc_ap,
const MultiDrvrNet *multi_drvr,
ArcDelayCalc *arc_delay_calc);
void annotateLoadDelays(Vertex *drvr_vertex,
const RiseFall *drvr_rf,
@@ -197,32 +209,7 @@ protected:
void findLatchEdgeDelays(Edge *edge);
void findCheckEdgeDelays(Edge *edge,
ArcDelayCalc *arc_delay_calc);
void findMultiDrvrGateDelay(MultiDrvrNet *multi_drvr,
const RiseFall *drvr_rf,
const Pvt *pvt,
const DcalcAnalysisPt *dcalc_ap,
ArcDelayCalc *arc_delay_calc,
// Return values.
ArcDelay &parallel_delay,
Slew &parallel_slew);
void parallelGateDelay(MultiDrvrNet *multi_drvr,
LibertyCell *drvr_cell,
const Pin *drvr_pin,
TimingArc *arc,
const Pvt *pvt,
const DcalcAnalysisPt *dcalc_ap,
const Slew from_slew,
Parasitic *drvr_parasitic,
float related_out_cap,
ArcDelayCalc *arc_delay_calc,
// Return values.
ArcDelay &gate_delay,
Slew &gate_slew);
void deleteMultiDrvrNets();
Slew edgeFromSlew(const Vertex *from_vertex,
const RiseFall *from_rf,
const Edge *edge,
const DcalcAnalysisPt *dcalc_ap);
Slew checkEdgeClkSlew(const Vertex *from_vertex,
const RiseFall *from_rf,
const DcalcAnalysisPt *dcalc_ap);
@@ -233,11 +220,6 @@ protected:
// Return values.
float &pin_cap,
float &wire_cap) const;
float loadCap(const Pin *drvr_pin,
MultiDrvrNet *multi_drvr,
const Parasitic *drvr_parasitic,
const RiseFall *rf,
const DcalcAnalysisPt *dcalc_ap) const;
// Observer for edge delay changes.
DelayCalcObserver *observer_;
@@ -277,4 +259,33 @@ public:
virtual void checkDelayChangedTo(Vertex *vertex) = 0;
};
// Nets with multiple drivers (tristate, bidirect or output).
// Cache net caps to prevent N^2 net pin walk.
class MultiDrvrNet
{
public:
MultiDrvrNet(VertexSet *drvrs);
~MultiDrvrNet();
const VertexSet *drvrs() const { return drvrs_; }
VertexSet *drvrs() { return drvrs_; }
bool parallelGates(const Network *network) const;
Vertex *dcalcDrvr() const { return dcalc_drvr_; }
void setDcalcDrvr(Vertex *drvr);
void netCaps(const RiseFall *rf,
const DcalcAnalysisPt *dcalc_ap,
// Return values.
float &pin_cap,
float &wire_cap,
float &fanout,
bool &has_net_load) const;
void findCaps(const Sdc *sdc);
private:
// Driver that triggers delay calculation for all the drivers on the net.
Vertex *dcalc_drvr_;
VertexSet *drvrs_;
// [drvr_rf->index][dcalc_ap->index]
vector<NetCaps> net_caps_;
};
} // namespace
+4 -8
View File
@@ -167,16 +167,14 @@ public:
const LibertyCell *cell,
const Pvt *pvt) const;
float scaleFactor(ScaleFactorType type,
int tr_index,
int rf_index,
const LibertyCell *cell,
const Pvt *pvt) const;
void setWireSlewDegradationTable(TableModel *model,
RiseFall *rf);
TableModel *wireSlewDegradationTable(const RiseFall *rf) const;
float degradeWireSlew(const LibertyCell *cell,
const RiseFall *rf,
const Pvt *pvt,
float degradeWireSlew(const RiseFall *rf,
float in_slew,
float wire_delay) const;
// Check for supported axis variables.
@@ -323,9 +321,7 @@ public:
void addDriverWaveform(DriverWaveform *driver_waveform);
protected:
float degradeWireSlew(const LibertyCell *cell,
const Pvt *pvt,
const TableModel *model,
float degradeWireSlew(const TableModel *model,
float in_slew,
float wire_delay) const;
@@ -925,7 +921,7 @@ public:
RiseFall *rf);
float scale(ScaleFactorType type,
ScaleFactorPvt pvt,
int tr_index);
int rf_index);
float scale(ScaleFactorType type,
ScaleFactorPvt pvt);
void setScale(ScaleFactorType type,
+10 -12
View File
@@ -23,9 +23,10 @@ namespace sta {
class GateLinearModel : public GateTimingModel
{
public:
GateLinearModel(float intrinsic, float resistance);
void gateDelay(const LibertyCell *cell,
const Pvt *pvt,
GateLinearModel(LibertyCell *cell,
float intrinsic,
float resistance);
void gateDelay(const Pvt *pvt,
float in_slew,
float load_cap,
float related_out_cap,
@@ -33,15 +34,13 @@ public:
// Return values.
ArcDelay &gate_delay,
Slew &drvr_slew) const override;
string reportGateDelay(const LibertyCell *cell,
const Pvt *pvt,
string reportGateDelay(const Pvt *pvt,
float in_slew,
float load_cap,
float related_out_cap,
bool pocv_enabled,
int digits) const override;
float driveResistance(const LibertyCell *cell,
const Pvt *pvt) const override;
float driveResistance(const Pvt *pvt) const override;
protected:
void setIsScaled(bool is_scaled) override;
@@ -53,17 +52,16 @@ protected:
class CheckLinearModel : public CheckTimingModel
{
public:
explicit CheckLinearModel(float intrinsic);
void checkDelay(const LibertyCell *cell,
const Pvt *pvt,
explicit CheckLinearModel(LibertyCell *cell,
float intrinsic);
void checkDelay(const Pvt *pvt,
float from_slew,
float to_slew,
float related_out_cap,
bool pocv_enabled,
// Return values.
ArcDelay &margin) const override;
string reportCheckDelay(const LibertyCell *cell,
const Pvt *pvt,
string reportCheckDelay(const Pvt *pvt,
float from_slew,
const char *from_slew_annotation,
float to_slew,
+2 -1
View File
@@ -827,7 +827,8 @@ public:
// Returns nullptr if set_operating_conditions has not been called.
OperatingConditions *operatingConditions(const MinMax *min_max);
// Instance specific process/voltage/temperature.
const Pvt *pvt(Instance *inst, const MinMax *min_max) const;
const Pvt *pvt(const Instance *inst,
const MinMax *min_max) const;
// Pvt may be shared among multiple instances.
void setPvt(const Instance *inst,
const MinMaxAll *min_max,
+15 -36
View File
@@ -51,15 +51,15 @@ tableVariableUnit(TableAxisVariable variable,
class GateTableModel : public GateTimingModel
{
public:
GateTableModel(TableModel *delay_model,
GateTableModel(LibertyCell *cell,
TableModel *delay_model,
TableModel *delay_sigma_models[EarlyLate::index_count],
TableModel *slew_model,
TableModel *slew_sigma_models[EarlyLate::index_count],
ReceiverModelPtr receiver_model,
OutputWaveforms *output_waveforms);
virtual ~GateTableModel();
void gateDelay(const LibertyCell *cell,
const Pvt *pvt,
void gateDelay(const Pvt *pvt,
float in_slew,
float load_cap,
float related_out_cap,
@@ -67,15 +67,13 @@ public:
// Return values.
ArcDelay &gate_delay,
Slew &drvr_slew) const override;
string reportGateDelay(const LibertyCell *cell,
const Pvt *pvt,
string reportGateDelay(const Pvt *pvt,
float in_slew,
float load_cap,
float related_out_cap,
bool pocv_enabled,
int digits) const override;
float driveResistance(const LibertyCell *cell,
const Pvt *pvt) const override;
float driveResistance(const Pvt *pvt) const override;
const TableModel *delayModel() const { return delay_model_; }
const TableModel *slewModel() const { return slew_model_; }
@@ -86,8 +84,7 @@ public:
static bool checkAxes(const TablePtr table);
protected:
void maxCapSlew(const LibertyCell *cell,
float in_slew,
void maxCapSlew(float in_slew,
const Pvt *pvt,
float &slew,
float &cap) const;
@@ -96,16 +93,12 @@ protected:
float load_cap,
float in_slew,
float related_out_cap) const;
float findValue(const LibertyLibrary *library,
const LibertyCell *cell,
const Pvt *pvt,
float findValue(const Pvt *pvt,
const TableModel *model,
float in_slew,
float load_cap,
float related_out_cap) const;
string reportTableLookup(const char *result_name,
const LibertyLibrary *library,
const LibertyCell *cell,
const Pvt *pvt,
const TableModel *model,
float in_slew,
@@ -133,19 +126,18 @@ protected:
class CheckTableModel : public CheckTimingModel
{
public:
explicit CheckTableModel(TableModel *model,
explicit CheckTableModel(LibertyCell *cell,
TableModel *model,
TableModel *sigma_models[EarlyLate::index_count]);
virtual ~CheckTableModel();
void checkDelay(const LibertyCell *cell,
const Pvt *pvt,
void checkDelay(const Pvt *pvt,
float from_slew,
float to_slew,
float related_out_cap,
bool pocv_enabled,
// Return values.
ArcDelay &margin) const override;
string reportCheckDelay(const LibertyCell *cell,
const Pvt *pvt,
string reportCheckDelay(const Pvt *pvt,
float from_slew,
const char *from_slew_annotation,
float to_slew,
@@ -160,9 +152,7 @@ public:
protected:
void setIsScaled(bool is_scaled) override;
float findValue(const LibertyLibrary *library,
const LibertyCell *cell,
const Pvt *pvt,
float findValue(const Pvt *pvt,
const TableModel *model,
float from_slew,
float to_slew,
@@ -179,8 +169,6 @@ protected:
float in_slew,
float related_out_cap) const;
string reportTableDelay(const char *result_name,
const LibertyLibrary *library,
const LibertyCell *cell,
const Pvt *pvt,
const TableModel *model,
float from_slew,
@@ -217,14 +205,12 @@ public:
float value2,
float value3) const;
// Table interpolated lookup with scale factor.
float findValue(const LibertyLibrary *library,
const LibertyCell *cell,
float findValue(const LibertyCell *cell,
const Pvt *pvt,
float value1,
float value2,
float value3) const;
string reportValue(const char *result_name,
const LibertyLibrary *library,
const LibertyCell *cell,
const Pvt *pvt,
float value1,
@@ -237,11 +223,9 @@ public:
Report *report) const;
protected:
float scaleFactor(const LibertyLibrary *library,
const LibertyCell *cell,
float scaleFactor(const LibertyCell *cell,
const Pvt *pvt) const;
string reportPvtScaleFactor(const LibertyLibrary *library,
const LibertyCell *cell,
string reportPvtScaleFactor(const LibertyCell *cell,
const Pvt *pvt,
int digits) const;
@@ -280,7 +264,6 @@ public:
float axis_value2,
float axis_value3) const;
virtual string reportValue(const char *result_name,
const LibertyLibrary *library,
const LibertyCell *cell,
const Pvt *pvt,
float value1,
@@ -306,7 +289,6 @@ public:
float axis_value2,
float axis_value3) const override;
string reportValue(const char *result_name,
const LibertyLibrary *library,
const LibertyCell *cell,
const Pvt *pvt,
float value1,
@@ -342,7 +324,6 @@ public:
float value2,
float value3) const override;
string reportValue(const char *result_name,
const LibertyLibrary *library,
const LibertyCell *cell,
const Pvt *pvt,
float value1,
@@ -389,7 +370,6 @@ public:
float value2,
float value3) const override;
string reportValue(const char *result_name,
const LibertyLibrary *library,
const LibertyCell *cell,
const Pvt *pvt,
float value1,
@@ -436,7 +416,6 @@ public:
float value2,
float value3) const override;
string reportValue(const char *result_name,
const LibertyLibrary *library,
const LibertyCell *cell,
const Pvt *pvt,
float value1,
+10 -13
View File
@@ -29,21 +29,21 @@ using std::string;
class TimingModel
{
public:
TimingModel(LibertyCell *cell);
virtual ~TimingModel() {}
protected:
virtual void setIsScaled(bool is_scaled) = 0;
friend class LibertyCell;
protected:
LibertyCell *cell_;
};
// Abstract base class for LinearModel and TableModel.
class GateTimingModel : public TimingModel
{
public:
GateTimingModel(LibertyCell *cell);
// Gate delay calculation.
virtual void gateDelay(const LibertyCell *cell,
const Pvt *pvt,
virtual void gateDelay(const Pvt *pvt,
float in_slew,
float load_cap,
float related_out_cap,
@@ -51,32 +51,29 @@ public:
// Return values.
ArcDelay &gate_delay,
Slew &drvr_slew) const = 0;
virtual string reportGateDelay(const LibertyCell *cell,
const Pvt *pvt,
virtual string reportGateDelay(const Pvt *pvt,
float in_slew,
float load_cap,
float related_out_cap,
bool pocv_enabled,
int digits) const = 0;
virtual float driveResistance(const LibertyCell *cell,
const Pvt *pvt) const = 0;
virtual float driveResistance(const Pvt *pvt) const = 0;
};
// Abstract base class for timing check timing models.
class CheckTimingModel : public TimingModel
{
public:
CheckTimingModel(LibertyCell *cell);
// Timing check margin delay calculation.
virtual void checkDelay(const LibertyCell *cell,
const Pvt *pvt,
virtual void checkDelay(const Pvt *pvt,
float from_slew,
float to_slew,
float related_out_cap,
bool pocv_enabled,
// Return values.
ArcDelay &margin) const = 0;
virtual string reportCheckDelay(const LibertyCell *cell,
const Pvt *pvt,
virtual string reportCheckDelay(const Pvt *pvt,
float from_slew,
const char *from_slew_annotation,
float to_slew,