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issue109 write_verilog seg fault 

Signed-off-by: James Cherry <cherry@parallaxsw.com>
This commit is contained in:
James Cherry 2024-10-19 16:30:59 -07:00
parent 900c762ddb
commit 221835137f
1 changed files with 19 additions and 17 deletions
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36
verilog/VerilogWriter.cc
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@ -411,22 +411,24 @@ VerilogWriter::writeAssigns(Instance *inst)
while (pin_iter->hasNext()) { while (pin_iter->hasNext()) {
Pin *pin = pin_iter->next(); Pin *pin = pin_iter->next();
Term *term = network_->term(pin); Term *term = network_->term(pin);
Net *net = network_->net(term); if (term) {
Port *port = network_->port(pin); Net *net = network_->net(term);
if (port Port *port = network_->port(pin);
&& (include_pwr_gnd_ if (port
|| !(network_->isPower(net) || network_->isGround(net))) && (include_pwr_gnd_
&& (network_->direction(port)->isAnyOutput() || !(network_->isPower(net) || network_->isGround(net)))
|| (include_pwr_gnd_ && network_->direction(port)->isPowerGround())) && (network_->direction(port)->isAnyOutput()
&& !stringEqual(network_->name(port), network_->name(net))) { || (include_pwr_gnd_ && network_->direction(port)->isPowerGround()))
// Port name is different from net name. && !stringEqual(network_->name(port), network_->name(net))) {
string port_vname = netVerilogName(network_->name(port), // Port name is different from net name.
network_->pathEscape()); string port_vname = netVerilogName(network_->name(port),
string net_vname = netVerilogName(network_->name(net), network_->pathEscape());
network_->pathEscape()); string net_vname = netVerilogName(network_->name(net),
fprintf(stream_, " assign %s = %s;\n", network_->pathEscape());
port_vname.c_str(), fprintf(stream_, " assign %s = %s;\n",
net_vname.c_str()); port_vname.c_str(),
net_vname.c_str());
}
} }
} }
delete pin_iter; delete pin_iter;
@ -434,7 +436,7 @@ VerilogWriter::writeAssigns(Instance *inst)
//////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////
// Walk the hierarch counting unconnected nets used to connect to // Walk the hierarchy counting unconnected nets used to connect to
// bus ports with concatenation. // bus ports with concatenation.
int int
VerilogWriter::findUnconnectedNetCount() VerilogWriter::findUnconnectedNetCount()