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https://github.com/The-OpenROAD-Project/OpenSTA.git
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issue109 write_verilog seg fault
Signed-off-by: James Cherry <[email protected]>
This commit is contained in:
+19
-17
@@ -411,22 +411,24 @@ VerilogWriter::writeAssigns(Instance *inst)
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while (pin_iter->hasNext()) {
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Pin *pin = pin_iter->next();
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Term *term = network_->term(pin);
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Net *net = network_->net(term);
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Port *port = network_->port(pin);
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if (port
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&& (include_pwr_gnd_
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|| !(network_->isPower(net) || network_->isGround(net)))
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&& (network_->direction(port)->isAnyOutput()
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|| (include_pwr_gnd_ && network_->direction(port)->isPowerGround()))
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&& !stringEqual(network_->name(port), network_->name(net))) {
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// Port name is different from net name.
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string port_vname = netVerilogName(network_->name(port),
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network_->pathEscape());
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string net_vname = netVerilogName(network_->name(net),
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network_->pathEscape());
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fprintf(stream_, " assign %s = %s;\n",
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port_vname.c_str(),
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net_vname.c_str());
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if (term) {
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Net *net = network_->net(term);
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Port *port = network_->port(pin);
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if (port
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&& (include_pwr_gnd_
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|| !(network_->isPower(net) || network_->isGround(net)))
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&& (network_->direction(port)->isAnyOutput()
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|| (include_pwr_gnd_ && network_->direction(port)->isPowerGround()))
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&& !stringEqual(network_->name(port), network_->name(net))) {
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// Port name is different from net name.
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string port_vname = netVerilogName(network_->name(port),
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network_->pathEscape());
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string net_vname = netVerilogName(network_->name(net),
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network_->pathEscape());
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fprintf(stream_, " assign %s = %s;\n",
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port_vname.c_str(),
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net_vname.c_str());
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}
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}
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}
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delete pin_iter;
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@@ -434,7 +436,7 @@ VerilogWriter::writeAssigns(Instance *inst)
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////////////////////////////////////////////////////////////////
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// Walk the hierarch counting unconnected nets used to connect to
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// Walk the hierarchy counting unconnected nets used to connect to
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// bus ports with concatenation.
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int
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VerilogWriter::findUnconnectedNetCount()
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