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OpenSTA
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Merge remote-tracking branch 'parallax/master' 

Signed-off-by: Matt Liberty <mliberty@precisioninno.com>
This commit is contained in:
Matt Liberty 2024-09-13 03:13:17 +00:00
parent 431856884a 86460dbd2d
commit 20925bb009
8 changed files with 60 additions and 56 deletions
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doc/OpenSTA.odt
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doc/OpenSTA.pdf
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4
include/sta/EquivCells.hh
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@ -73,8 +73,4 @@ bool
equivCellSequentials(const LibertyCell *cell1,
const LibertyCell *cell2);
bool
equivCellFootprints(const LibertyCell *cell1,
const LibertyCell *cell2);
} // namespace

10
liberty/EquivCells.cc
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@ -325,8 +325,7 @@ equivCells(const LibertyCell *cell1,
&& equivCellPgPorts(cell1, cell2)
&& equivCellSequentials(cell1, cell2)
&& equivCellStatetables(cell1, cell2)
&& equivCellTimingArcSets(cell1, cell2)
&& equivCellFootprints(cell1, cell2);
&& equivCellTimingArcSets(cell1, cell2);
}
bool
@ -526,11 +525,4 @@ equivCellTimingArcSets(const LibertyCell *cell1,
}
}
bool
equivCellFootprints(const LibertyCell *cell1,
const LibertyCell *cell2)
{
return stringEqIf(cell1->footprint(), cell2->footprint());
}
} // namespace

6
liberty/Liberty.cc
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@ -768,8 +768,8 @@ LibertyLibrary::makeCornerMap(LibertyCell *cell1,
cell2->name());
}
for (auto arc_set1 : cell1->timing_arc_sets_) {
auto arc_set2 = cell2->findTimingArcSet(arc_set1);
for (TimingArcSet *arc_set1 : cell1->timing_arc_sets_) {
TimingArcSet *arc_set2 = cell2->findTimingArcSet(arc_set1);
if (arc_set2) {
if (link) {
const TimingArcSeq &arcs1 = arc_set1->arcs();
@ -789,7 +789,7 @@ LibertyLibrary::makeCornerMap(LibertyCell *cell1,
report->warn(1111, "cell %s/%s %s -> %s timing group %s not found in cell %s/%s.",
cell1->library()->name(),
cell1->name(),
arc_set1->from()->name(),
arc_set1->from() ? arc_set1->from()->name() : "",
arc_set1->to()->name(),
arc_set1->role()->asString(),
cell2->library()->name(),

25
sdc/Sdc.tcl
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@ -408,25 +408,22 @@ proc current_design { {design ""} } {
# Generic get_* filter.
proc filter_objs { filter objects filter_function object_type } {
set filter_regexp1 {@?([a-zA-Z_]+) *(==|!=|=~|!~) *([0-9a-zA-Z_\*]+)}
set filter_regexp1 {@?([a-zA-Z_]+) *((==|!=|=~|!~) *([0-9a-zA-Z_\*]+))?}
set filter_or_regexp "($filter_regexp1) *\\|\\| *($filter_regexp1)"
set filter_and_regexp "($filter_regexp1) *&& *($filter_regexp1)"
set filtered_objects {}
# Ignore sub-exprs in filter_regexp1 for expr2 match var.
if { [regexp $filter_or_regexp $filter ignore expr1 \
ignore ignore ignore expr2] } {
regexp $filter_regexp1 $expr1 ignore attr_name op arg
set filtered_objects1 [$filter_function $attr_name $op $arg $objects]
regexp $filter_regexp1 $expr2 ignore attr_name op arg
set filtered_objects2 [$filter_function $attr_name $op $arg $objects]
if { [regexp $filter_or_regexp $filter ignore expr1 ignore ignore ignore ignore expr2] } {
set filtered_objects1 [filter_objs $expr1 $objects $filter_function $object_type]
set filtered_objects2 [filter_objs $expr2 $objects $filter_function $object_type]
set filtered_objects [concat $filtered_objects1 $filtered_objects2]
} elseif { [regexp $filter_and_regexp $filter ignore expr1 \
ignore ignore ignore expr2] } {
regexp $filter_regexp1 $expr1 ignore attr_name op arg
set filtered_objects [$filter_function $attr_name $op $arg $objects]
regexp $filter_regexp1 $expr2 ignore attr_name op arg
set filtered_objects [$filter_function $attr_name $op $arg $filtered_objects]
} elseif { [regexp $filter_regexp1 $filter ignore attr_name op arg] } {
} elseif { [regexp $filter_and_regexp $filter ignore expr1 ignore ignore ignore ignore expr2] } {
set filtered_objects [filter_objs $expr1 $objects $filter_function $object_type]
set filtered_objects [filter_objs $expr2 $filtered_objects $filter_function $object_type]
} elseif { [regexp $filter_regexp1 $filter ignore attr_name ignore op arg] } {
# If no op/arg, use <attr_name>==1 by default.
set op [expr {($op == "") ? "==" : $op}]
set arg [expr {($arg == "") ? "1" : $arg}]
set filtered_objects [$filter_function $attr_name $op $arg $objects]
} else {
sta_error 350 "unsupported $object_type -filter expression."

35
test/get_filter.ok
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@ -1,25 +1,34 @@
get_cells
[get_cells -filter liberty_cell==BUFx2_ASAP7_75t_R *]
u1
get_clocks
[get_clocks -filter is_virtual==0 *]
clk
get_clocks 2
[get_clocks -filter is_virtual==1 *]
vclk
get_lib_cells
[get_clocks -filter is_virtual *]
vclk
[get_clocks -filter is_virtual&&is_generated *]
[get_clocks -filter is_virtual&&is_generated==0 *]
vclk
[get_clocks -filter is_virtual||is_generated *]
vclk
[get_clocks -filter is_virtual==0||is_generated *]
clk
[get_lib_cells -filter is_buffer==1 *]
asap7_small/BUFx2_ASAP7_75t_R
get_lib_cells 2
[get_lib_cells -filter is_inverter==0 *]
asap7_small/AND2x2_ASAP7_75t_R
asap7_small/BUFx2_ASAP7_75t_R
asap7_small/DFFHQx4_ASAP7_75t_R
get_lib_pins
[get_lib_pins -filter direction==input BUFx2_ASAP7_75t_R/*]
A
get_lib_pins 2
[get_lib_pins -filter direction==output BUFx2_ASAP7_75t_R/*]
Y
get_libs
[get_libs -filter name==asap7_small *]
asap7_small
get_nets
[get_nets -filter name=~*q *]
r1q
r2q
get_pins
[get_pins -filter direction==input *]
r1/CLK
r1/D
r2/CLK
@ -29,17 +38,17 @@ r3/D
u1/A
u2/A
u2/B
get_pins 2
[get_pins -filter direction==output *]
r1/Q
r2/Q
r3/Q
u1/Y
u2/Y
get_ports
[get_ports -filter direction==input *]
clk1
clk2
clk3
in1
in2
get_ports 2
[get_ports -filter direction==output *]
out

36
test/get_filter.tcl
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@ -6,29 +6,39 @@ create_clock -name clk -period 500 {clk1 clk2 clk3}
create_clock -name vclk -period 1000
# Test filters for each SDC command
puts "get_cells"
puts {[get_cells -filter liberty_cell==BUFx2_ASAP7_75t_R *]}
report_object_full_names [get_cells -filter liberty_cell==BUFx2_ASAP7_75t_R *]
puts "get_clocks"
puts {[get_clocks -filter is_virtual==0 *]}
report_object_full_names [get_clocks -filter is_virtual==0 *]
puts "get_clocks 2"
puts {[get_clocks -filter is_virtual==1 *]}
report_object_full_names [get_clocks -filter is_virtual==1 *]
puts "get_lib_cells"
puts {[get_clocks -filter is_virtual *]}
report_object_full_names [get_clocks -filter is_virtual *]
puts {[get_clocks -filter is_virtual&&is_generated *]}
report_object_full_names [get_clocks -filter is_virtual&&is_generated *]
puts {[get_clocks -filter is_virtual&&is_generated==0 *]}
report_object_full_names [get_clocks -filter is_virtual&&is_generated==0 *]
puts {[get_clocks -filter is_virtual||is_generated *]}
report_object_full_names [get_clocks -filter is_virtual||is_generated *]
puts {[get_clocks -filter is_virtual==0||is_generated *]}
report_object_full_names [get_clocks -filter is_virtual==0||is_generated *]
puts {[get_lib_cells -filter is_buffer==1 *]}
report_object_full_names [get_lib_cells -filter is_buffer==1 *]
puts "get_lib_cells 2"
puts {[get_lib_cells -filter is_inverter==0 *]}
report_object_full_names [get_lib_cells -filter is_inverter==0 *]
puts "get_lib_pins"
puts {[get_lib_pins -filter direction==input BUFx2_ASAP7_75t_R/*]}
report_object_full_names [get_lib_pins -filter direction==input BUFx2_ASAP7_75t_R/*]
puts "get_lib_pins 2"
puts {[get_lib_pins -filter direction==output BUFx2_ASAP7_75t_R/*]}
report_object_full_names [get_lib_pins -filter direction==output BUFx2_ASAP7_75t_R/*]
puts "get_libs"
puts {[get_libs -filter name==asap7_small *]}
report_object_full_names [get_libs -filter name==asap7_small *]
puts "get_nets"
puts {[get_nets -filter name=~*q *]}
report_object_full_names [get_nets -filter name=~*q *]
puts "get_pins"
puts {[get_pins -filter direction==input *]}
report_object_full_names [get_pins -filter direction==input *]
puts "get_pins 2"
puts {[get_pins -filter direction==output *]}
report_object_full_names [get_pins -filter direction==output *]
puts "get_ports"
puts {[get_ports -filter direction==input *]}
report_object_full_names [get_ports -filter direction==input *]
puts "get_ports 2"
puts {[get_ports -filter direction==output *]}
report_object_full_names [get_ports -filter direction==output *]