Merge remote-tracking branch 'upstream/master'
Signed-off-by: Matt Liberty <mliberty@precisioninno.com>
This commit is contained in:
commit
1f9adb4b96
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@ -110,7 +110,6 @@ public:
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virtual float sourceClkOffset(const StaState *sta) const = 0;
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virtual float sourceClkOffset(const StaState *sta) const = 0;
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virtual Delay sourceClkLatency(const StaState *sta) const;
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virtual Delay sourceClkLatency(const StaState *sta) const;
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virtual Delay sourceClkInsertionDelay(const StaState *sta) const;
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virtual Delay sourceClkInsertionDelay(const StaState *sta) const;
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virtual Delay sourceClkDelay(const StaState *sta) const;
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virtual PathVertex *targetClkPath();
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virtual PathVertex *targetClkPath();
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virtual const PathVertex *targetClkPath() const;
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virtual const PathVertex *targetClkPath() const;
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virtual const Clock *targetClk(const StaState *sta) const;
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virtual const Clock *targetClk(const StaState *sta) const;
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@ -188,10 +187,6 @@ public:
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protected:
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protected:
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PathEnd(Path *path);
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PathEnd(Path *path);
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void clkPath(PathVertex *path,
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const StaState *sta,
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// Return value.
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PathVertex &clk_path);
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static float checkNonInterClkUncertainty(const PathVertex *tgt_clk_path,
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static float checkNonInterClkUncertainty(const PathVertex *tgt_clk_path,
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const ClockEdge *tgt_clk_edge,
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const ClockEdge *tgt_clk_edge,
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const TimingRole *check_role,
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const TimingRole *check_role,
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@ -327,7 +322,6 @@ public:
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virtual TimingArc *checkArc() const { return check_arc_; }
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virtual TimingArc *checkArc() const { return check_arc_; }
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virtual int exceptPathCmp(const PathEnd *path_end,
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virtual int exceptPathCmp(const PathEnd *path_end,
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const StaState *sta) const;
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const StaState *sta) const;
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virtual Delay sourceClkDelay(const StaState *sta) const;
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virtual Delay clkSkew(const StaState *sta);
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virtual Delay clkSkew(const StaState *sta);
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protected:
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protected:
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@ -338,6 +332,7 @@ protected:
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MultiCyclePath *mcp,
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MultiCyclePath *mcp,
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Crpr crpr,
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Crpr crpr,
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bool crpr_valid);
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bool crpr_valid);
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Delay sourceClkDelay(const StaState *sta) const;
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TimingArc *check_arc_;
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TimingArc *check_arc_;
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Edge *check_edge_;
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Edge *check_edge_;
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@ -517,6 +512,10 @@ protected:
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MultiCyclePath *mcp,
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MultiCyclePath *mcp,
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Crpr crpr,
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Crpr crpr,
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bool crpr_valid);
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bool crpr_valid);
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void clkPath(PathVertex *path,
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const StaState *sta,
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// Return value.
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PathVertex &clk_path);
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Arrival requiredTimeNoCrpr(const StaState *sta) const;
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Arrival requiredTimeNoCrpr(const StaState *sta) const;
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// setup uses zero cycle default
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// setup uses zero cycle default
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virtual int setupDefaultCycles() const { return 0; }
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virtual int setupDefaultCycles() const { return 0; }
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@ -156,12 +156,6 @@ PathEnd::sourceClkInsertionDelay(const StaState *) const
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return delay_zero;
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return delay_zero;
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}
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}
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Delay
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PathEnd::sourceClkDelay(const StaState *) const
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{
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return delay_zero;
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}
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const Clock *
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const Clock *
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PathEnd::targetClk(const StaState *) const
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PathEnd::targetClk(const StaState *) const
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{
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{
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@ -290,45 +284,6 @@ PathEnd::exceptPathCmp(const PathEnd *path_end,
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return 1;
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return 1;
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}
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}
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// PathExpanded::expand() and PathExpanded::clkPath().
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// Similar to srcClkPath but for PathVertex's.
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void
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PathEnd::clkPath(PathVertex *path,
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const StaState *sta,
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// Return value.
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PathVertex &clk_path)
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{
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PathVertex p(path);
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while (!p.isNull()) {
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PathVertex prev_path;
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TimingArc *prev_arc;
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p.prevPath(sta, prev_path, prev_arc);
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if (p.isClock(sta)) {
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clk_path = p;
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return;
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}
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if (prev_arc) {
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TimingRole *prev_role = prev_arc->role();
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if (prev_role == TimingRole::regClkToQ()
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|| prev_role == TimingRole::latchEnToQ()) {
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p.prevPath(sta, prev_path, prev_arc);
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clk_path = prev_path;
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return;
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}
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else if (prev_role == TimingRole::latchDtoQ()) {
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const Latches *latches = sta->latches();
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Edge *prev_edge = p.prevEdge(prev_arc, sta);
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PathVertex enable_path;
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latches->latchEnablePath(&p, prev_edge, enable_path);
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clk_path = enable_path;
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return;
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}
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}
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p = prev_path;
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}
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}
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////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////
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Delay
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Delay
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@ -1059,12 +1014,21 @@ PathEndCheck::exceptPathCmp(const PathEnd *path_end,
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return cmp;
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return cmp;
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}
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}
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Delay
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PathEndCheck::clkSkew(const StaState *sta)
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{
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commonClkPessimism(sta);
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return sourceClkDelay(sta) - targetClkDelay(sta) - crpr_;
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}
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Delay
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Delay
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PathEndCheck::sourceClkDelay(const StaState *sta) const
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PathEndCheck::sourceClkDelay(const StaState *sta) const
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{
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{
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ClkInfo *src_clk_info = path_.tag(sta)->clkInfo();
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PathExpanded expanded(&path_, sta);
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const PathVertex src_clk_path(src_clk_info->crprClkPath(), sta);
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PathRef src_clk_path;
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expanded.clkPath(src_clk_path);
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if (!src_clk_path.isNull()) {
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if (!src_clk_path.isNull()) {
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ClkInfo *src_clk_info = path_.tag(sta)->clkInfo();
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if (src_clk_info->isPropagated()) {
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if (src_clk_info->isPropagated()) {
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// Propagated clock. Propagated arrival is seeded with insertion delay.
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// Propagated clock. Propagated arrival is seeded with insertion delay.
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Arrival clk_arrival = src_clk_path.arrival(sta);
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Arrival clk_arrival = src_clk_path.arrival(sta);
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@ -1080,13 +1044,6 @@ PathEndCheck::sourceClkDelay(const StaState *sta) const
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return 0.0;
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return 0.0;
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}
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}
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Delay
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PathEndCheck::clkSkew(const StaState *sta)
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{
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commonClkPessimism(sta);
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return sourceClkDelay(sta) - targetClkDelay(sta) - crpr_;
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}
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////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////
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PathEndLatchCheck::PathEndLatchCheck(Path *path,
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PathEndLatchCheck::PathEndLatchCheck(Path *path,
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@ -1610,6 +1567,45 @@ PathEndDataCheck::PathEndDataCheck(DataCheck *check,
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clkPath(data_clk_path, sta, clk_path_);
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clkPath(data_clk_path, sta, clk_path_);
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}
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}
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// PathExpanded::expand() and PathExpanded::clkPath().
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void
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PathEndDataCheck::clkPath(PathVertex *path,
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const StaState *sta,
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// Return value.
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PathVertex &clk_path)
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{
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PathVertex p(path);
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while (!p.isNull()) {
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PathVertex prev_path;
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TimingArc *prev_arc;
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p.prevPath(sta, prev_path, prev_arc);
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if (p.isClock(sta)) {
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clk_path = p;
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return;
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}
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if (prev_arc) {
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TimingRole *prev_role = prev_arc->role();
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if (prev_role == TimingRole::regClkToQ()
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|| prev_role == TimingRole::latchEnToQ()) {
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p.prevPath(sta, prev_path, prev_arc);
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clk_path = prev_path;
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return;
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}
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else if (prev_role == TimingRole::latchDtoQ()) {
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const Latches *latches = sta->latches();
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Edge *prev_edge = p.prevEdge(prev_arc, sta);
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PathVertex enable_path;
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latches->latchEnablePath(&p, prev_edge, enable_path);
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clk_path = enable_path;
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return;
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}
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}
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p = prev_path;
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}
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}
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PathEndDataCheck::PathEndDataCheck(DataCheck *check,
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PathEndDataCheck::PathEndDataCheck(DataCheck *check,
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Path *data_path,
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Path *data_path,
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PathVertex *data_clk_path,
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PathVertex *data_clk_path,
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@ -69,7 +69,7 @@ proc show_cmd_args { cmd } {
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}
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}
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set arglist $rest
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set arglist $rest
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} else {
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} else {
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report_line $line
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report_line "$line $arglist"
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break
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break
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}
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}
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}
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}
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@ -396,7 +396,7 @@ define_cmd_args "report_checks" \
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[-sort_by_slack]\
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[-sort_by_slack]\
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[-path_group group_name]\
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[-path_group group_name]\
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[-format full|full_clock|full_clock_expanded|short|end|summary]\
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[-format full|full_clock|full_clock_expanded|short|end|summary]\
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[-fields [capacitance|slew|input_pin|net]]\
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[-fields capacitance|slew|input_pin|net]\
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[-digits digits]\
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[-digits digits]\
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[-no_line_splits]\
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[-no_line_splits]\
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[> filename] [>> filename]}
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[> filename] [>> filename]}
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@ -1227,6 +1227,10 @@ using namespace sta;
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Tcl_SetObjResult(interp, obj);
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Tcl_SetObjResult(interp, obj);
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}
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}
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%typemap(out) Delay {
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Tcl_SetObjResult(interp,Tcl_NewDoubleObj(delayAsFloat($1)));
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}
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%typemap(out) Arrival {
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%typemap(out) Arrival {
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Tcl_SetObjResult(interp,Tcl_NewDoubleObj(delayAsFloat($1)));
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Tcl_SetObjResult(interp,Tcl_NewDoubleObj(delayAsFloat($1)));
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}
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}
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@ -1247,6 +1251,10 @@ using namespace sta;
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Tcl_SetObjResult(interp,Tcl_NewDoubleObj(delayAsFloat($1)));
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Tcl_SetObjResult(interp,Tcl_NewDoubleObj(delayAsFloat($1)));
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}
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}
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%typemap(out) Crpr {
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Tcl_SetObjResult(interp,Tcl_NewDoubleObj(delayAsFloat($1)));
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}
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%typemap(in) PathGroupNameSet* {
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%typemap(in) PathGroupNameSet* {
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$1 = tclListSetConstChar($input, interp);
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$1 = tclListSetConstChar($input, interp);
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}
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}
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