do not check slew limits on ideal clk nets
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9cacb0cfd9
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1dbae09fb7
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@ -101,6 +101,7 @@ public:
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virtual float ceff(Edge *edge,
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TimingArc *arc,
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const DcalcAnalysisPt *dcalc_ap);
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virtual bool isIdealClk(const Vertex *vertex) = 0;
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// Precedence:
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// SDF annotation
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// Liberty library
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@ -197,7 +197,7 @@ protected:
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bool setIdealClks(const Vertex *vertex,
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ClockSet *clks);
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ClockSet *idealClks(const Vertex *vertex);
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bool isIdealClk(const Vertex *vertex);
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virtual bool isIdealClk(const Vertex *vertex);
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Slew idealClkSlew(const Vertex *vertex,
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const RiseFall *rf,
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const MinMax *min_max);
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@ -23,6 +23,7 @@
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#include "StaState.hh"
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#include "DcalcAnalysisPt.hh"
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#include "Corner.hh"
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#include "GraphDelayCalc.hh"
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#include "PathVertex.hh"
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#include "Search.hh"
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#include "CheckSlewLimits.hh"
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@ -173,66 +174,40 @@ CheckSlewLimits::findLimit(const Pin *pin,
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// Return values.
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float &limit,
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bool &exists) const
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{
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exists = false;
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const Network *network = sta_->network();
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Sdc *sdc = sta_->sdc();
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bool is_clk = sta_->search()->isClock(vertex);
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// Look for clock slew limits.
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ClockSet clks;
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clockDomains(vertex, clks);
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ClockSet::Iterator clk_iter(clks);
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while (clk_iter.hasNext()) {
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Clock *clk = clk_iter.next();
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PathClkOrData clk_data = is_clk ? PathClkOrData::clk : PathClkOrData::data;
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float clk_limit;
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bool clk_limit_exists;
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sdc->slewLimit(clk, rf, clk_data, min_max,
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clk_limit, clk_limit_exists);
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if (clk_limit_exists
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&& (!exists
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|| min_max->compare(limit, clk_limit))) {
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// Use the tightest clock limit.
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limit = clk_limit;
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exists = true;
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}
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}
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if (!exists) {
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// Default to top ("design") limit.
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exists = top_limit_exists_;
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limit = top_limit_;
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if (network->isTopLevelPort(pin)) {
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Port *port = network->port(pin);
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float port_limit;
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bool port_limit_exists;
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sdc->slewLimit(port, min_max, port_limit, port_limit_exists);
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// Use the tightest limit.
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if (port_limit_exists
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if (!sta_->graphDelayCalc()->isIdealClk(vertex)) {
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const Network *network = sta_->network();
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Sdc *sdc = sta_->sdc();
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bool is_clk = sta_->search()->isClock(vertex);
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// Look for clock slew limits.
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ClockSet clks;
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clockDomains(vertex, clks);
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ClockSet::Iterator clk_iter(clks);
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while (clk_iter.hasNext()) {
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Clock *clk = clk_iter.next();
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PathClkOrData clk_data = is_clk ? PathClkOrData::clk : PathClkOrData::data;
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float clk_limit;
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bool clk_limit_exists;
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sdc->slewLimit(clk, rf, clk_data, min_max,
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clk_limit, clk_limit_exists);
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if (clk_limit_exists
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&& (!exists
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|| min_max->compare(limit, port_limit))) {
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limit = port_limit;
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|| min_max->compare(limit, clk_limit))) {
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// Use the tightest clock limit.
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limit = clk_limit;
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exists = true;
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}
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}
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else {
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float pin_limit;
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bool pin_limit_exists;
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sdc->slewLimit(pin, min_max,
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pin_limit, pin_limit_exists);
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// Use the tightest limit.
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if (pin_limit_exists
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&& (!exists
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|| min_max->compare(limit, pin_limit))) {
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limit = pin_limit;
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exists = true;
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}
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float port_limit;
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bool port_limit_exists;
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LibertyPort *port = network->libertyPort(pin);
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if (port) {
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port->slewLimit(min_max, port_limit, port_limit_exists);
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if (!exists) {
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// Default to top ("design") limit.
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exists = top_limit_exists_;
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limit = top_limit_;
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if (network->isTopLevelPort(pin)) {
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Port *port = network->port(pin);
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float port_limit;
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bool port_limit_exists;
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sdc->slewLimit(port, min_max, port_limit, port_limit_exists);
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// Use the tightest limit.
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if (port_limit_exists
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&& (!exists
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@ -241,6 +216,33 @@ CheckSlewLimits::findLimit(const Pin *pin,
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exists = true;
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}
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}
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else {
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float pin_limit;
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bool pin_limit_exists;
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sdc->slewLimit(pin, min_max,
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pin_limit, pin_limit_exists);
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// Use the tightest limit.
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if (pin_limit_exists
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&& (!exists
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|| min_max->compare(limit, pin_limit))) {
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limit = pin_limit;
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exists = true;
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}
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float port_limit;
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bool port_limit_exists;
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LibertyPort *port = network->libertyPort(pin);
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if (port) {
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port->slewLimit(min_max, port_limit, port_limit_exists);
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// Use the tightest limit.
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if (port_limit_exists
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&& (!exists
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|| min_max->compare(limit, port_limit))) {
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limit = port_limit;
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exists = true;
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}
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}
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}
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}
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}
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}
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