Merge remote-tracking branch 'upstream/master'

This commit is contained in:
Matt Liberty 2025-11-18 06:35:29 +00:00
commit 1d6e79a327
15 changed files with 159 additions and 17 deletions

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@ -24,6 +24,8 @@
#include "ArcDelayCalc.hh"
#include <cstdlib>
#include "Units.hh"
#include "Liberty.hh"
#include "TimingArc.hh"

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@ -355,7 +355,7 @@ public:
const Network *network) = 0;
virtual void connectPinAfter(PinSet *,
Network *network) = 0;
virtual void disconnectPinBefore(const Pin *pin,
virtual void deletePinBefore(const Pin *pin,
Network *network) = 0;
protected:
@ -415,7 +415,7 @@ public:
const Network *) {}
virtual void connectPinAfter(PinSet *,
Network *) {}
virtual void disconnectPinBefore(const Pin *,
virtual void deletePinBefore(const Pin *,
Network *);
void deleteInstance(const Instance *inst,
const Network *network);
@ -537,7 +537,7 @@ public:
virtual size_t objectCount() const;
virtual void connectPinAfter(PinSet *drvrs,
Network *network);
virtual void disconnectPinBefore(const Pin *pin,
virtual void deletePinBefore(const Pin *pin,
Network *network);
void deleteInstance(const Instance *inst,
const Network *network);

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@ -1027,7 +1027,7 @@ public:
void removeGraphAnnotations();
// Network edit before/after methods.
void disconnectPinBefore(const Pin *pin);
void deletePinBefore(const Pin *pin);
void connectPinAfter(const Pin *pin);
void clkHpinDisablesChanged(const Pin *pin);
void makeClkHpinDisable(const Clock *clk,
@ -1115,6 +1115,7 @@ protected:
void recordMergeHash(ExceptionPath *exception, ExceptionPt *missing_pt);
void recordMergeHashes(ExceptionPath *exception);
void unrecordExceptionFirstPts(ExceptionPath *exception);
void unrecordExceptionPins(ExceptionPath *exception);
void unrecordExceptionClks(ExceptionPath *exception,
ClockSet *clks,
ClockExceptionsMap &exception_map);

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@ -1226,7 +1226,8 @@ LibertyCell::bufferPorts(// Return values.
}
output = port;
}
else if (!dir->isPowerGround()) {
else if (!port->isPwrGnd()) {
// Invalid direction.
input = nullptr;
output = nullptr;
break;

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@ -24,6 +24,7 @@
#include "TableModel.hh"
#include <cmath>
#include <string>
#include "Error.hh"

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@ -1166,7 +1166,7 @@ ExceptionFromTo::deleteInstance(const Instance *inst,
}
void
ExceptionFromTo::disconnectPinBefore(const Pin *pin,
ExceptionFromTo::deletePinBefore(const Pin *pin,
Network *network)
{
deletePin(pin, network);
@ -2080,7 +2080,7 @@ ExceptionThru::makePinEdges(const Pin *pin,
}
void
ExceptionThru::disconnectPinBefore(const Pin *pin,
ExceptionThru::deletePinBefore(const Pin *pin,
Network *network)
{
deletePin(pin, network);

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@ -4880,6 +4880,8 @@ Sdc::findMergeMatch(ExceptionPath *exception)
void
Sdc::deleteExceptions()
{
for (ExceptionPath *exception : exceptions_)
delete exception;
exceptions_.clear();
exception_id_ = 0;
@ -4964,6 +4966,7 @@ Sdc::unrecordException(ExceptionPath *exception)
{
unrecordMergeHashes(exception);
unrecordExceptionFirstPts(exception);
unrecordExceptionPins(exception);
exceptions_.erase(exception);
}
@ -5022,6 +5025,22 @@ Sdc::unrecordExceptionFirstPts(ExceptionPath *exception)
}
}
void
Sdc::unrecordExceptionPins(ExceptionPath *exception)
{
ExceptionFrom *from = exception->from();
if (from)
unrecordExceptionPins(exception, from->pins(), pin_exceptions_);
ExceptionThruSeq *thrus = exception->thrus();
if (thrus) {
for (ExceptionThru *thru : *thrus)
unrecordExceptionPins(exception, thru->pins(), pin_exceptions_);
}
ExceptionTo *to = exception->to();
if (to)
unrecordExceptionPins(exception, to->pins(), pin_exceptions_);
}
void
Sdc::unrecordExceptionClks(ExceptionPath *exception,
ClockSet *clks,
@ -5666,22 +5685,22 @@ Sdc::connectPinAfter(const Pin *pin)
}
void
Sdc::disconnectPinBefore(const Pin *pin)
Sdc::deletePinBefore(const Pin *pin)
{
auto itr = pin_exceptions_.find(pin);
if (itr != pin_exceptions_.end()) {
for (ExceptionPath *exception : itr->second) {
ExceptionFrom *from = exception->from();
if (from)
from->disconnectPinBefore(pin, network_);
from->deletePinBefore(pin, network_);
ExceptionTo *to = exception->to();
if (to)
to->disconnectPinBefore(pin, network_);
to->deletePinBefore(pin, network_);
ExceptionPt *first_pt = exception->firstPt();
ExceptionThruSeq *thrus = exception->thrus();
if (thrus) {
for (ExceptionThru *thru : *exception->thrus()) {
thru->disconnectPinBefore(pin, network_);
thru->deletePinBefore(pin, network_);
if (thru == first_pt)
recordExceptionEdges(exception, thru->edges(),
first_thru_edge_exceptions_);

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@ -4477,7 +4477,6 @@ Sta::disconnectPinBefore(const Pin *pin)
sdc_network_->pathName(pin),
sdc_network_->pathName(network_->net(pin)));
parasitics_->disconnectPinBefore(pin, network_);
sdc_->disconnectPinBefore(pin);
sim_->disconnectPinBefore(pin);
if (graph_) {
if (network_->isDriver(pin)) {
@ -4663,6 +4662,7 @@ Sta::deletePinBefore(const Pin *pin)
}
}
}
sdc_->deletePinBefore(pin);
sim_->deletePinBefore(pin);
clk_network_->deletePinBefore(pin);
power_->deletePinBefore(pin);

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@ -0,0 +1,59 @@
Warning: disconnect_mcp_pin.tcl line 15, 'u0/A' is not a valid endpoint.
Warning: disconnect_mcp_pin.tcl line 16, 'u1/A' is not a valid endpoint.
Warning: disconnect_mcp_pin.tcl line 17, 'u0/A' is not a valid endpoint.
Warning: disconnect_mcp_pin.tcl line 18, 'u1/A' is not a valid endpoint.
Startpoint: data_in[1] (input port clocked by clk)
Endpoint: u1 (falling edge-triggered data to data check clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
500.00 500.00 clock clk (rise edge)
0.00 500.00 clock network delay (ideal)
10.00 510.00 ^ input external delay
0.00 510.00 ^ data_in[1] (in)
0.00 510.00 ^ u1/A (BUFx2_ASAP7_75t_R)
510.00 data arrival time
750.00 750.00 clock clk (fall edge)
0.00 750.00 clock network delay (propagated)
0.00 750.00 clock reconvergence pessimism
750.00 v clk (in)
-10.00 740.00 data check setup time
740.00 data required time
---------------------------------------------------------
740.00 data required time
-510.00 data arrival time
---------------------------------------------------------
230.00 slack (MET)
No paths found.
Startpoint: data_in[1] (input port clocked by clk)
Endpoint: u1 (falling edge-triggered data to data check clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
500.00 500.00 clock clk (rise edge)
0.00 500.00 clock network delay (ideal)
10.00 510.00 ^ input external delay
0.00 510.00 ^ data_in[1] (in)
0.00 510.00 ^ u1/A (BUFx2_ASAP7_75t_R)
510.00 data arrival time
750.00 750.00 clock clk (fall edge)
0.00 750.00 clock network delay (propagated)
0.00 750.00 clock reconvergence pessimism
750.00 v clk (in)
-10.00 740.00 data check setup time
740.00 data required time
---------------------------------------------------------
740.00 data required time
-510.00 data arrival time
---------------------------------------------------------
230.00 slack (MET)

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@ -0,0 +1,29 @@
# disconnect/disconnect pin set_multicycle_path
read_liberty asap7_small.lib.gz
read_verilog disconnect_mcp_pin.v
link_design top
create_clock -name clk -period 500 clk
set_input_delay -clock clk 10 data_in[*]
# This SDC defines setup and hold time requirements for data pins
# relative to a clock, typical for a source-synchronous interface.
set_data_check -from clk -to [get_pins u0/A] -setup 10
set_data_check -from clk -to [get_pins u0/A] -hold 10
set_data_check -from clk -to [get_pins u1/A] -setup 10
set_data_check -from clk -to [get_pins u1/A] -hold 10
set_multicycle_path -end -setup 1 -to [get_pins u0/A]
set_multicycle_path -end -setup 1 -to [get_pins u1/A]
set_multicycle_path -start -hold 0 -to [get_pins u0/A]
set_multicycle_path -start -hold 0 -to [get_pins u1/A]
report_checks -to u1/A
disconnect_pin data_in[1] u1/A
report_checks -to u1/A
connect_pin data_in[1] u1/A
report_checks -to u1/A

11
test/disconnect_mcp_pin.v Normal file
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@ -0,0 +1,11 @@
module top (clk, clkout, data_in, data_out);
input clk;
output clkout;
input [1:0] data_in;
output [1:0] data_out;
// Anchor buffers on the source-synchronous interface IOs
BUFx2_ASAP7_75t_R clkbuf0 (.A(clk), .Y(clkout));
BUFx2_ASAP7_75t_R u0 (.A(data_in[0]), .Y(data_out[0]));
BUFx2_ASAP7_75t_R u1 (.A(data_in[1]), .Y(data_out[1]));
endmodule // top

1
test/get_is_buffer.ok Normal file
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@ -0,0 +1 @@
buf_inst

5
test/get_is_buffer.tcl Normal file
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@ -0,0 +1,5 @@
# is_buffer property
read_liberty ../examples/sky130hd_tt.lib.gz
read_verilog get_is_buffer.v
link_design dut
report_object_full_names [get_cells -filter is_buffer]

11
test/get_is_buffer.v Normal file
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@ -0,0 +1,11 @@
module dut (
input A,
output Y
);
sky130_fd_sc_hd__buf_2 buf_inst (
.A(A),
.X(Y)
);
endmodule

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@ -138,7 +138,9 @@ record_example_tests {
}
record_sta_tests {
disconnect_mcp_pin
get_filter
get_is_buffer
get_is_memory
get_lib_pins_of_objects
get_noargs