VerilogWriter using instead of include for LibertyCell

include/sta/VerilogWriter.hh

@@ -17,12 +17,13 @@
 #pragma once
 
 #include <vector>
-#include "LibertyClass.hh"
 
 namespace sta {
 
 using std::vector;
+
 class Network;
+class LibertyCell;
 
 void
 writeVerilog(const char *filename,

verilog/Verilog.i

@@ -25,7 +25,6 @@
 using sta::Sta;
 using sta::NetworkReader;
 using sta::readVerilogFile;
-using sta::LibertyCellSeq;
 
 %}