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VerilogWriter using instead of include for LibertyCell

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This commit is contained in:
James Cherry
2020-07-18 09:12:38 -07:00
parent 9882f9d938
commit 1c8f1ec9fc
2 changed files with 2 additions and 2 deletions
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include/sta/VerilogWriter.hh
+2 -1
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@@ -17,12 +17,13 @@
#pragma once
#include <vector>
#include "LibertyClass.hh"
namespace sta {
using std::vector;
class Network;
class LibertyCell;
void
writeVerilog(const char *filename,