set_min/max_delay illegal endpoint warning
Signed-off-by: James Cherry <cherry@parallaxsw.com>
This commit is contained in:
parent
6df4cdc794
commit
1c45b89879
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@ -186,7 +186,7 @@ proc edge_disable_reason { edge } {
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}
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}
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if { [$edge is_disabled_preset_clear] } {
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if { [$edge is_disabled_preset_clear] } {
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if { $disables != "" } { append disables ", " }
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if { $disables != "" } { append disables ", " }
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append disables "timing_enable_preset_clear_arcs"
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append disables "sta_preset_clear_arcs_enabled"
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}
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}
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return $disables
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return $disables
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}
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}
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@ -777,7 +777,7 @@ public:
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NetSet *nets,
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NetSet *nets,
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InstanceSet *insts,
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InstanceSet *insts,
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const RiseFallBoth *rf);
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const RiseFallBoth *rf);
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bool exceptionToInvalid(const Pin *pin);
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bool isExceptionEndpoint(const Pin *pin);
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// Make an exception -to specification.
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// Make an exception -to specification.
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ExceptionTo *makeExceptionTo(PinSet *pins,
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ExceptionTo *makeExceptionTo(PinSet *pins,
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ClockSet *clks,
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ClockSet *clks,
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67
sdc/Sdc.cc
67
sdc/Sdc.cc
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@ -3799,6 +3799,22 @@ Sdc::makeExceptionFrom(PinSet *from_pins,
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return nullptr;
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return nullptr;
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}
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}
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bool
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Sdc::isExceptionStartpoint(const Pin *pin) const
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{
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Net *net = network_->net(pin);
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const LibertyPort *port = network_->libertyPort(pin);
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return ((network_->isTopLevelPort(pin)
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&& network_->direction(pin)->isAnyInput())
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|| (port && port->isRegClk())
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|| (port && port->isLatchData()))
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// Pins connected to power/ground are invalid.
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&& !(net
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&& (network_->isPower(net)
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|| network_->isGround(net)))
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&& !network_->isHierarchical(pin);
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}
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ExceptionThru *
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ExceptionThru *
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Sdc::makeExceptionThru(PinSet *pins,
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Sdc::makeExceptionThru(PinSet *pins,
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NetSet *nets,
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NetSet *nets,
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@ -3833,31 +3849,31 @@ Sdc::makeExceptionTo(PinSet *pins,
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// Valid endpoints include gated clock enables which are not
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// Valid endpoints include gated clock enables which are not
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// known until clock arrivals are determined.
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// known until clock arrivals are determined.
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bool
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bool
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Sdc::exceptionToInvalid(const Pin *pin)
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Sdc::isExceptionEndpoint(const Pin *pin)
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{
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{
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Net *net = network_->net(pin);
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Net *net = network_->net(pin);
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// Floating pins are invalid.
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bool has_checks = false;
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if ((net == nullptr
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const LibertyPort *port = network_->libertyPort(pin);
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&& !(network_->isTopLevelPort(pin)
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|| network_->direction(pin)->isInternal()))
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|| (net
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// Pins connected to power/ground are invalid.
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&& (network_->isPower(net)
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|| network_->isGround(net)))
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// Hierarchical pins are invalid.
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|| network_->isHierarchical(pin))
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return true;
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// Register/latch Q pins are invalid.
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LibertyPort *port = network_->libertyPort(pin);
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if (port) {
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if (port) {
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// Look for timing checks to the pin witihout using the graph because
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// it may not exist.
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LibertyCell *cell = port->libertyCell();
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LibertyCell *cell = port->libertyCell();
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for (TimingArcSet *arc_set : cell->timingArcSets(nullptr, port)) {
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for (TimingArcSet *arc_set : cell->timingArcSets(nullptr, port)) {
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const TimingRole *role = arc_set->role();
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if (arc_set->role()->isTimingCheck()) {
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if (role->genericRole() == TimingRole::regClkToQ())
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has_checks = true;
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return true;
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break;
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}
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}
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}
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}
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}
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return false;
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return ((network_->isTopLevelPort(pin)
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&& network_->direction(pin)->isAnyOutput())
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|| has_checks
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|| (port && port->isLatchData()))
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// Pins connected to power/ground are invalid.
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&& !(net
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&& (network_->isPower(net)
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|| network_->isGround(net)))
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&& !network_->isHierarchical(pin);
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}
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}
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void
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void
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@ -3941,21 +3957,6 @@ Sdc::unrecordPathDelayInternalFrom(ExceptionPath *exception)
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}
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}
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}
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}
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bool
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Sdc::isExceptionStartpoint(const Pin *pin) const
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{
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Net *net = network_->net(pin);
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const LibertyPort *port = network_->libertyPort(pin);
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return ((network_->isTopLevelPort(pin)
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&& network_->direction(pin)->isAnyInput())
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|| (port && port->isRegClk())
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|| (port && port->isLatchData()))
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// Pins connected to power/ground are invalid.
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&& !(net
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&& (network_->isPower(net)
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|| network_->isGround(net)));
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}
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bool
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bool
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Sdc::pathDelayFrom(const Pin *pin)
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Sdc::pathDelayFrom(const Pin *pin)
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{
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{
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@ -2085,7 +2085,7 @@ Sta::checkExceptionToPins(ExceptionTo *to,
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PinSet::Iterator pin_iter(to->pins());
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PinSet::Iterator pin_iter(to->pins());
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while (pin_iter.hasNext()) {
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while (pin_iter.hasNext()) {
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const Pin *pin = pin_iter.next();
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const Pin *pin = pin_iter.next();
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if (sdc_->exceptionToInvalid(pin)) {
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if (!sdc_->isExceptionEndpoint(pin)) {
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if (line)
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if (line)
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report_->fileWarn(1551, file, line, "'%s' is not a valid endpoint.",
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report_->fileWarn(1551, file, line, "'%s' is not a valid endpoint.",
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cmd_network_->pathName(pin));
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cmd_network_->pathName(pin));
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@ -113,9 +113,8 @@ VisitPathEnds::visitClkedPathEnds(const Pin *pin,
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else if (vertex->hasChecks())
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else if (vertex->hasChecks())
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visitCheckEnd(pin, vertex, path, end_rf, path_ap, filtered, visitor,
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visitCheckEnd(pin, vertex, path, end_rf, path_ap, filtered, visitor,
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is_constrained);
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is_constrained);
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else if (!sdc_->exceptionToInvalid(pin)
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else if (!filtered
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&& (!filtered
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|| search_->matchesFilter(path, nullptr)) {
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|| search_->matchesFilter(path, nullptr))) {
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PathDelay *path_delay = pathDelayTo(path, pin, end_rf, path_min_max);
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PathDelay *path_delay = pathDelayTo(path, pin, end_rf, path_min_max);
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if (path_delay) {
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if (path_delay) {
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PathEndPathDelay path_end(path_delay, path, this);
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PathEndPathDelay path_end(path_delay, path, this);
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@ -231,8 +230,7 @@ VisitPathEnds::visitCheckEnd(const Pin *pin,
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}
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}
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}
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}
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}
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}
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if (!check_clked
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if (!check_clked)
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&& !sdc_->exceptionToInvalid(pin))
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visitCheckEndUnclked(pin, vertex, path, end_rf, path_ap, filtered,
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visitCheckEndUnclked(pin, vertex, path, end_rf, path_ap, filtered,
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visitor, is_constrained);
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visitor, is_constrained);
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}
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}
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