write_verilog -remove_cells support non-liberty cells

Signed-off-by: James Cherry <cherry@parallaxsw.com>

include/sta/VerilogWriter.hh

@@ -16,20 +16,15 @@
 
 #pragma once
 
-#include <vector>
+#include "NetworkClass.hh"
 
 namespace sta {
 
-using std::vector;
-
-class Network;
-class LibertyCell;
-
 void
 writeVerilog(const char *filename,
 	     bool sort,
 	     bool include_pwr_gnd,
-	     vector<LibertyCell*> *remove_cells,
+	     CellSeq *remove_cells,
 	     Network *network);
 
 } // namespace

tcl/Cmds.tcl

@@ -286,6 +286,12 @@ proc parse_libcell_inst_net_arg { objects libcells_var insts_var nets_var } {
   get_object_args $objects {} libcells {} {} insts {} {} nets {} {}
 }
 
+proc parse_cell_arg { objects } {
+  set cells {}
+  get_object_args $objects {} {} {} cells {} {} {} {} {} {}
+  return $cells
+}
+
 proc parse_cell_port_args { objects cells_var ports_var } {
   upvar 1 $cells_var cells
   upvar 1 $ports_var ports

tcl/StaTcl.i

@@ -184,13 +184,6 @@ tclListSeqLibertyLibrary(Tcl_Obj *const source,
   return tclListSeq<LibertyLibrary*>(source, SWIGTYPE_p_LibertyLibrary, interp);
 }
 
-vector<LibertyCell*> *
-tclListSeqLibertyCell(Tcl_Obj *const source,
-		      Tcl_Interp *interp)
-{
-  return tclListSeq<LibertyCell*>(source, SWIGTYPE_p_LibertyCell, interp);
-}
-
 template <class TYPE>
 Set<TYPE> *
 tclListSet(Tcl_Obj *const source,
@@ -428,6 +421,10 @@ using namespace sta;
   Tcl_SetObjResult(interp, list);
 }
 
+%typemap(in) CellSeq* {
+  $1 = tclListSeq<Cell*>($input, SWIGTYPE_p_Cell, interp);
+}
+
 %typemap(out) TmpCellSeq* {
   Tcl_Obj *list = Tcl_NewListObj(0, nullptr);
   CellSeq *cells = $1;
@@ -441,10 +438,6 @@ using namespace sta;
   delete cells;
 }
 
-%typemap(in) vector<LibertyCell*> * {
-  $1 = tclListSeqLibertyCell($input, interp);
-}
-
 %typemap(out) LibertyCellSeq* {
   Tcl_Obj *list = Tcl_NewListObj(0, nullptr);
   LibertyCellSeq *cells = $1;

verilog/Verilog.i

@@ -53,7 +53,7 @@ void
 write_verilog_cmd(const char *filename,
 		  bool sort,
 		  bool include_pwr_gnd,
-		  vector<LibertyCell*> *remove_cells)
+		  CellSeq *remove_cells)
 {
   // This does NOT want the SDC (cmd) network because it wants
   // to see the sta internal names.

verilog/Verilog.tcl

@@ -32,7 +32,7 @@ proc write_verilog { args } {
 
   set remove_cells {}
   if { [info exists keys(-remove_cells)] } {
-    set remove_cells [sta::parse_libcell_arg $keys(-remove_cells)]
+    set remove_cells [parse_cell_arg $keys(-remove_cells)]
   }
   set sort [info exists flags(-sort)]
   set include_pwr_gnd [info exists flags(-include_pwr_gnd)]

verilog/VerilogWriter.cc

@@ -38,7 +38,7 @@ public:
   VerilogWriter(const char *filename,
 		bool sort,
 		bool include_pwr_gnd_pins,
-		vector<LibertyCell*> *remove_cells,
+		CellSeq *remove_cells,
 		FILE *stream,
 		Network *network);
   void writeModule(Instance *inst);
@@ -70,7 +70,7 @@ protected:
   const char *filename_;
   bool sort_;
   bool include_pwr_gnd_;
-  LibertyCellSet remove_cells_;
+  CellSet remove_cells_;
   FILE *stream_;
   Network *network_;
 
@@ -83,7 +83,7 @@ void
 writeVerilog(const char *filename,
 	     bool sort,
 	     bool include_pwr_gnd_pins,
-	     vector<LibertyCell*> *remove_cells,
+	     CellSeq *remove_cells,
 	     Network *network)
 {
   if (network->topInstance()) {
@@ -102,7 +102,7 @@ writeVerilog(const char *filename,
 VerilogWriter::VerilogWriter(const char *filename,
 			     bool sort,
 			     bool include_pwr_gnd_pins,
-			     vector<LibertyCell*> *remove_cells,
+			     CellSeq *remove_cells,
 			     FILE *stream,
 			     Network *network) :
   filename_(filename),
@@ -113,7 +113,7 @@ VerilogWriter::VerilogWriter(const char *filename,
   unconnected_net_index_(1)
 {
   if (remove_cells) {
-    for(LibertyCell *lib_cell : *remove_cells)
+    for(Cell *lib_cell : *remove_cells)
       remove_cells_.insert(lib_cell);
   }
 }
@@ -293,8 +293,7 @@ void
 VerilogWriter::writeChild(Instance *child)
 {
   Cell *child_cell = network_->cell(child);
-  LibertyCell *lib_cell = network_->libertyCell(child_cell);
+  if (!remove_cells_.hasKey(child_cell)) {
-  if (!remove_cells_.hasKey(lib_cell)) {
     const char *child_name = network_->name(child);
     const char *child_vname = instanceVerilogName(child_name,
 						  network_->pathEscape());
@@ -451,8 +450,7 @@ VerilogWriter::findChildNCcount(Instance *child)
 {
   int nc_count = 0;
   Cell *child_cell = network_->cell(child);
-  LibertyCell *lib_cell = network_->libertyCell(child_cell);
+  if (!remove_cells_.hasKey(child_cell)) {
-  if (!remove_cells_.hasKey(lib_cell)) {
     CellPortIterator *port_iter = network_->portIterator(child_cell);
     while (port_iter->hasNext()) {
       Port *port = port_iter->next();