report_check_types -max_fanout respect set_driving_cell fanout limit
Signed-off-by: James Cherry <cherry@parallaxsw.com>
This commit is contained in:
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e34a3465b1
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17bd47049d
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@ -919,7 +919,7 @@ Sdc::fanoutLimit(Cell *cell,
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float &fanout,
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float &fanout,
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bool &exists)
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bool &exists)
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{
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{
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fanout = 0.0;
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fanout = min_max->initValue();
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MinMaxFloatValues values;
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MinMaxFloatValues values;
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cell_fanout_limit_map_.findKey(cell, values, exists);
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cell_fanout_limit_map_.findKey(cell, values, exists);
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if (exists)
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if (exists)
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@ -20,6 +20,7 @@
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#include "Liberty.hh"
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#include "Liberty.hh"
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#include "Network.hh"
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#include "Network.hh"
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#include "Sdc.hh"
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#include "Sdc.hh"
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#include "InputDrive.hh"
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#include "Sim.hh"
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#include "Sim.hh"
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#include "PortDirection.hh"
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#include "PortDirection.hh"
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#include "Graph.hh"
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#include "Graph.hh"
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@ -84,7 +85,7 @@ CheckFanoutLimits::checkFanout(const Pin *pin,
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float &slack) const
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float &slack) const
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{
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{
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fanout = 0.0;
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fanout = 0.0;
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limit = 0.0;
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limit = min_max->initValue();
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slack = MinMax::min()->initValue();
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slack = MinMax::min()->initValue();
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float limit1;
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float limit1;
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@ -106,10 +107,8 @@ CheckFanoutLimits::findLimit(const Pin *pin,
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const Network *network = sta_->network();
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const Network *network = sta_->network();
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Sdc *sdc = sta_->sdc();
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Sdc *sdc = sta_->sdc();
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// Default to top ("design") limit.
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limit = min_max->initValue();
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Cell *top_cell = network->cell(network->topInstance());
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exists = false;
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sdc->fanoutLimit(top_cell, min_max,
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limit, exists);
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float limit1;
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float limit1;
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bool exists1;
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bool exists1;
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@ -122,8 +121,38 @@ CheckFanoutLimits::findLimit(const Pin *pin,
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limit = limit1;
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limit = limit1;
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exists = true;
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exists = true;
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}
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}
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InputDrive *drive = sdc->findInputDrive(port);
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if (drive) {
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for (auto min_max : MinMax::range()) {
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for (auto rf : RiseFall::range()) {
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LibertyCell *cell;
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LibertyPort *from_port;
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float *from_slews;
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LibertyPort *to_port;
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drive->driveCell(rf, min_max, cell, from_port, from_slews, to_port);
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if (to_port) {
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to_port->fanoutLimit(min_max, limit1, exists1);
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if (!exists1
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&& min_max == MinMax::max()
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&& to_port->direction()->isAnyOutput())
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to_port->libertyLibrary()->defaultMaxFanout(limit1, exists1);
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if (exists1
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&& (!exists
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|| min_max->compare(limit, limit1))) {
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limit = limit1;
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exists = true;
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}
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}
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}
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}
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}
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}
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}
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else {
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else {
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// Default to top ("design") limit.
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Cell *top_cell = network->cell(network->topInstance());
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sdc->fanoutLimit(top_cell, min_max,
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limit, exists);
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Cell *cell = network->cell(network->instance(pin));
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Cell *cell = network->cell(network->instance(pin));
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sdc->fanoutLimit(cell, min_max,
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sdc->fanoutLimit(cell, min_max,
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limit1, exists1);
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limit1, exists1);
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@ -175,30 +204,28 @@ CheckFanoutLimits::fanoutLoad(const Pin *pin) const
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{
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{
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float fanout = 0;
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float fanout = 0;
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const Network *network = sta_->network();
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const Network *network = sta_->network();
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Net *net = network->net(pin);
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NetConnectedPinIterator *pin_iter = network->connectedPinIterator(pin);
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if (net) {
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while (pin_iter->hasNext()) {
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NetPinIterator *pin_iter = network->pinIterator(net);
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Pin *fanout_pin = pin_iter->next();
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while (pin_iter->hasNext()) {
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if (network->isLoad(fanout_pin)
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Pin *pin = pin_iter->next();
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&& !network->isTopLevelPort(fanout_pin)) {
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if (network->isLoad(pin)) {
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LibertyPort *port = network->libertyPort(fanout_pin);
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LibertyPort *port = network->libertyPort(pin);
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if (port) {
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if (port) {
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float fanout_load;
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float fanout_load;
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bool exists;
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bool exists;
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port->fanoutLoad(fanout_load, exists);
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port->fanoutLoad(fanout_load, exists);
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if (!exists) {
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if (!exists) {
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LibertyLibrary *lib = port->libertyLibrary();
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LibertyLibrary *lib = port->libertyLibrary();
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lib->defaultFanoutLoad(fanout_load, exists);
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lib->defaultFanoutLoad(fanout_load, exists);
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}
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}
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if (exists)
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if (exists)
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fanout += fanout_load;
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fanout += fanout_load;
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}
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else
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fanout += 1;
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}
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}
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else
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fanout += 1;
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}
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}
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delete pin_iter;
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}
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}
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delete pin_iter;
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return fanout;
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return fanout;
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}
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}
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@ -288,8 +315,8 @@ CheckFanoutLimits::checkPin(Pin *pin)
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const Sim *sim = sta_->sim();
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const Sim *sim = sta_->sim();
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const Sdc *sdc = sta_->sdc();
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const Sdc *sdc = sta_->sdc();
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const Graph *graph = sta_->graph();
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const Graph *graph = sta_->graph();
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Vertex *vertex = graph->pinLoadVertex(pin);
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Vertex *vertex = graph->pinDrvrVertex(pin);
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return network->direction(pin)->isAnyOutput()
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return network->isDriver(pin)
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&& !sim->logicZeroOne(pin)
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&& !sim->logicZeroOne(pin)
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&& !sdc->isDisabled(pin)
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&& !sdc->isDisabled(pin)
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&& !(vertex && sta_->isIdealClock(pin));
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&& !(vertex && sta_->isIdealClock(pin));
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