report_check_types -max_fanout respect set_driving_cell fanout limit

Signed-off-by: James Cherry <cherry@parallaxsw.com>
This commit is contained in:
James Cherry 2021-10-22 10:51:20 -07:00
parent e34a3465b1
commit 17bd47049d
2 changed files with 56 additions and 29 deletions

View File

@ -919,7 +919,7 @@ Sdc::fanoutLimit(Cell *cell,
float &fanout, float &fanout,
bool &exists) bool &exists)
{ {
fanout = 0.0; fanout = min_max->initValue();
MinMaxFloatValues values; MinMaxFloatValues values;
cell_fanout_limit_map_.findKey(cell, values, exists); cell_fanout_limit_map_.findKey(cell, values, exists);
if (exists) if (exists)

View File

@ -20,6 +20,7 @@
#include "Liberty.hh" #include "Liberty.hh"
#include "Network.hh" #include "Network.hh"
#include "Sdc.hh" #include "Sdc.hh"
#include "InputDrive.hh"
#include "Sim.hh" #include "Sim.hh"
#include "PortDirection.hh" #include "PortDirection.hh"
#include "Graph.hh" #include "Graph.hh"
@ -84,7 +85,7 @@ CheckFanoutLimits::checkFanout(const Pin *pin,
float &slack) const float &slack) const
{ {
fanout = 0.0; fanout = 0.0;
limit = 0.0; limit = min_max->initValue();
slack = MinMax::min()->initValue(); slack = MinMax::min()->initValue();
float limit1; float limit1;
@ -106,10 +107,8 @@ CheckFanoutLimits::findLimit(const Pin *pin,
const Network *network = sta_->network(); const Network *network = sta_->network();
Sdc *sdc = sta_->sdc(); Sdc *sdc = sta_->sdc();
// Default to top ("design") limit. limit = min_max->initValue();
Cell *top_cell = network->cell(network->topInstance()); exists = false;
sdc->fanoutLimit(top_cell, min_max,
limit, exists);
float limit1; float limit1;
bool exists1; bool exists1;
@ -122,8 +121,38 @@ CheckFanoutLimits::findLimit(const Pin *pin,
limit = limit1; limit = limit1;
exists = true; exists = true;
} }
InputDrive *drive = sdc->findInputDrive(port);
if (drive) {
for (auto min_max : MinMax::range()) {
for (auto rf : RiseFall::range()) {
LibertyCell *cell;
LibertyPort *from_port;
float *from_slews;
LibertyPort *to_port;
drive->driveCell(rf, min_max, cell, from_port, from_slews, to_port);
if (to_port) {
to_port->fanoutLimit(min_max, limit1, exists1);
if (!exists1
&& min_max == MinMax::max()
&& to_port->direction()->isAnyOutput())
to_port->libertyLibrary()->defaultMaxFanout(limit1, exists1);
if (exists1
&& (!exists
|| min_max->compare(limit, limit1))) {
limit = limit1;
exists = true;
}
}
}
}
}
} }
else { else {
// Default to top ("design") limit.
Cell *top_cell = network->cell(network->topInstance());
sdc->fanoutLimit(top_cell, min_max,
limit, exists);
Cell *cell = network->cell(network->instance(pin)); Cell *cell = network->cell(network->instance(pin));
sdc->fanoutLimit(cell, min_max, sdc->fanoutLimit(cell, min_max,
limit1, exists1); limit1, exists1);
@ -175,13 +204,12 @@ CheckFanoutLimits::fanoutLoad(const Pin *pin) const
{ {
float fanout = 0; float fanout = 0;
const Network *network = sta_->network(); const Network *network = sta_->network();
Net *net = network->net(pin); NetConnectedPinIterator *pin_iter = network->connectedPinIterator(pin);
if (net) {
NetPinIterator *pin_iter = network->pinIterator(net);
while (pin_iter->hasNext()) { while (pin_iter->hasNext()) {
Pin *pin = pin_iter->next(); Pin *fanout_pin = pin_iter->next();
if (network->isLoad(pin)) { if (network->isLoad(fanout_pin)
LibertyPort *port = network->libertyPort(pin); && !network->isTopLevelPort(fanout_pin)) {
LibertyPort *port = network->libertyPort(fanout_pin);
if (port) { if (port) {
float fanout_load; float fanout_load;
bool exists; bool exists;
@ -198,7 +226,6 @@ CheckFanoutLimits::fanoutLoad(const Pin *pin) const
} }
} }
delete pin_iter; delete pin_iter;
}
return fanout; return fanout;
} }
@ -288,8 +315,8 @@ CheckFanoutLimits::checkPin(Pin *pin)
const Sim *sim = sta_->sim(); const Sim *sim = sta_->sim();
const Sdc *sdc = sta_->sdc(); const Sdc *sdc = sta_->sdc();
const Graph *graph = sta_->graph(); const Graph *graph = sta_->graph();
Vertex *vertex = graph->pinLoadVertex(pin); Vertex *vertex = graph->pinDrvrVertex(pin);
return network->direction(pin)->isAnyOutput() return network->isDriver(pin)
&& !sim->logicZeroOne(pin) && !sim->logicZeroOne(pin)
&& !sdc->isDisabled(pin) && !sdc->isDisabled(pin)
&& !(vertex && sta_->isIdealClock(pin)); && !(vertex && sta_->isIdealClock(pin));