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OL1467 Segfault during writing timing model for mutlti-corner 

Signed-off-by: James Cherry <cherry@parallaxsw.com>
This commit is contained in:
James Cherry 2022-11-02 13:58:10 -07:00
parent 902957de1e
commit 10371720f1
1 changed files with 23 additions and 19 deletions
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42
search/MakeTimingModel.cc
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@ -344,11 +344,13 @@ MakeTimingModel::makeSetupHoldTimingArcs(const Pin *input_pin,
LibertyPort *input_port = modelPort(input_pin);
for (const Pin *clk_pin : clk_edge->clock()->pins()) {
LibertyPort *clk_port = modelPort(clk_pin);
RiseFall *clk_rf = clk_edge->transition();
TimingRole *role = setup ? TimingRole::setup() : TimingRole::hold();
lib_builder_->makeFromTransitionArcs(cell_, clk_port,
input_port, nullptr,
clk_rf, role, attrs);
if (clk_port) {
RiseFall *clk_rf = clk_edge->transition();
TimingRole *role = setup ? TimingRole::setup() : TimingRole::hold();
lib_builder_->makeFromTransitionArcs(cell_, clk_port,
input_port, nullptr,
clk_rf, role, attrs);
}
}
}
}
@ -422,20 +424,22 @@ MakeTimingModel::findClkedOutputPaths()
RiseFallMinMax &delays = clk_edge_delay.second;
for (const Pin *clk_pin : clk_edge->clock()->pins()) {
LibertyPort *clk_port = modelPort(clk_pin);
RiseFall *clk_rf = clk_edge->transition();
TimingArcAttrsPtr attrs = nullptr;
for (RiseFall *output_rf : RiseFall::range()) {
float delay = delays.value(output_rf, min_max_) - clk_edge->time();
TimingModel *gate_model = makeGateModelTable(output_pin, delay, output_rf);
if (attrs == nullptr)
attrs = std::make_shared<TimingArcAttrs>();
attrs->setModel(output_rf, gate_model);
}
if (attrs) {
lib_builder_->makeFromTransitionArcs(cell_, clk_port,
output_port, nullptr,
clk_rf, TimingRole::regClkToQ(),
attrs);
if (clk_port) {
RiseFall *clk_rf = clk_edge->transition();
TimingArcAttrsPtr attrs = nullptr;
for (RiseFall *output_rf : RiseFall::range()) {
float delay = delays.value(output_rf, min_max_) - clk_edge->time();
TimingModel *gate_model = makeGateModelTable(output_pin, delay, output_rf);
if (attrs == nullptr)
attrs = std::make_shared<TimingArcAttrs>();
attrs->setModel(output_rf, gate_model);
}
if (attrs) {
lib_builder_->makeFromTransitionArcs(cell_, clk_port,
output_port, nullptr,
clk_rf, TimingRole::regClkToQ(),
attrs);
}
}
}
}