VerilogNamespace use string_view
Signed-off-by: James Cherry <cherry@parallaxsw.com>
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@ -25,25 +25,26 @@
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#pragma once
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#pragma once
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#include <string>
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#include <string>
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#include <string_view>
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namespace sta {
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namespace sta {
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std::string
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std::string
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cellVerilogName(std::string sta_name);
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cellVerilogName(std::string_view sta_name);
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std::string
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std::string
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instanceVerilogName(std::string sta_name);
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instanceVerilogName(std::string_view sta_name);
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std::string
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std::string
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netVerilogName(std::string sta_name);
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netVerilogName(std::string_view sta_name);
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std::string
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std::string
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portVerilogName(std::string sta_name);
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portVerilogName(std::string_view sta_name);
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std::string
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std::string
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moduleVerilogToSta(std::string sta_name);
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moduleVerilogToSta(std::string_view sta_name);
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std::string
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std::string
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instanceVerilogToSta(std::string sta_name);
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instanceVerilogToSta(std::string_view sta_name);
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std::string
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std::string
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netVerilogToSta(std::string sta_name);
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netVerilogToSta(std::string_view sta_name);
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std::string
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std::string
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portVerilogToSta(std::string sta_name);
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portVerilogToSta(std::string_view sta_name);
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} // namespace
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} // namespace
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@ -34,26 +34,26 @@ namespace sta {
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constexpr char verilog_escape = '\\';
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constexpr char verilog_escape = '\\';
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static std::string
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static std::string
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staToVerilog(std::string sta_name);
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staToVerilog(std::string_view sta_name);
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static std::string
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static std::string
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staToVerilog2(std::string sta_name);
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staToVerilog2(std::string_view sta_name);
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static std::string
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static std::string
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verilogToSta(const std::string verilog_name);
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verilogToSta(const std::string_view verilog_name);
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std::string
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std::string
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cellVerilogName(std::string sta_name)
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cellVerilogName(std::string_view sta_name)
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{
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{
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return staToVerilog(sta_name);
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return staToVerilog(sta_name);
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}
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}
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std::string
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std::string
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instanceVerilogName(std::string sta_name)
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instanceVerilogName(std::string_view sta_name)
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{
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{
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return staToVerilog(sta_name);
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return staToVerilog(sta_name);
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}
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}
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std::string
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std::string
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netVerilogName(std::string sta_name)
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netVerilogName(std::string_view sta_name)
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{
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{
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bool is_bus;
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bool is_bus;
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std::string bus_name;
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std::string bus_name;
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@ -69,13 +69,20 @@ netVerilogName(std::string sta_name)
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}
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}
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std::string
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std::string
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portVerilogName(std::string sta_name)
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portVerilogName(std::string_view sta_name)
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{
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{
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return staToVerilog2(sta_name);
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return staToVerilog2(sta_name);
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}
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}
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// <cctype> functions expect a value representable as unsigned char or EOF.
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static bool
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isAlnumUnderscore(char ch)
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{
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return std::isalnum(static_cast<unsigned char>(ch)) != 0 || ch == '_';
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}
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static std::string
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static std::string
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staToVerilog(std::string sta_name)
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staToVerilog(std::string_view sta_name)
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{
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{
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// Leave room for leading escape and trailing space if the name
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// Leave room for leading escape and trailing space if the name
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// needs to be escaped.
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// needs to be escaped.
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@ -87,14 +94,18 @@ staToVerilog(std::string sta_name)
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char ch = sta_name[i];
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char ch = sta_name[i];
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if (ch == verilog_escape) {
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if (ch == verilog_escape) {
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escaped = true;
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escaped = true;
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char next_ch = sta_name[i + 1];
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if (i + 1 < sta_length) {
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if (next_ch == verilog_escape) {
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char next_ch = sta_name[i + 1];
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escaped_name += next_ch;
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if (next_ch == verilog_escape) {
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i++;
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escaped_name += next_ch;
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i++;
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}
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}
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}
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else
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escaped_name += ch;
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}
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}
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else {
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else {
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if ((!(isalnum(ch) || ch == '_')))
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if (!isAlnumUnderscore(ch))
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escaped = true;
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escaped = true;
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escaped_name += ch;
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escaped_name += ch;
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}
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}
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@ -105,11 +116,11 @@ staToVerilog(std::string sta_name)
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return escaped_name;
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return escaped_name;
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}
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}
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else
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else
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return sta_name;
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return std::string(sta_name);
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}
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}
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static std::string
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static std::string
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staToVerilog2(std::string sta_name)
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staToVerilog2(std::string_view sta_name)
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{
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{
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constexpr char bus_brkt_left = '[';
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constexpr char bus_brkt_left = '[';
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constexpr char bus_brkt_right = ']';
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constexpr char bus_brkt_right = ']';
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@ -123,16 +134,19 @@ staToVerilog2(std::string sta_name)
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char ch = sta_name[i];
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char ch = sta_name[i];
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if (ch == verilog_escape) {
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if (ch == verilog_escape) {
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escaped = true;
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escaped = true;
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char next_ch = sta_name[i + 1];
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if (i + 1 < sta_length) {
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if (next_ch == verilog_escape) {
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char next_ch = sta_name[i + 1];
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escaped_name += next_ch;
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if (next_ch == verilog_escape) {
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i++;
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escaped_name += next_ch;
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i++;
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}
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}
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}
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else
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escaped_name += ch;
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}
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}
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else {
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else {
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bool is_brkt = (ch == bus_brkt_left || ch == bus_brkt_right);
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bool is_brkt = (ch == bus_brkt_left || ch == bus_brkt_right);
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if ((!(isalnum(ch) || ch == '_') && !is_brkt)
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if ((!isAlnumUnderscore(ch) && !is_brkt) || is_brkt)
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|| is_brkt)
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escaped = true;
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escaped = true;
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escaped_name += ch;
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escaped_name += ch;
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}
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}
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@ -143,45 +157,49 @@ staToVerilog2(std::string sta_name)
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return escaped_name;
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return escaped_name;
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}
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}
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else
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else
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return sta_name;
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return std::string(sta_name);
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}
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}
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////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////
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std::string
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std::string
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moduleVerilogToSta(std::string module_name)
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moduleVerilogToSta(std::string_view module_name)
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{
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{
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return verilogToSta(module_name);
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return verilogToSta(module_name);
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}
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}
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std::string
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std::string
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instanceVerilogToSta(std::string inst_name)
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instanceVerilogToSta(std::string_view inst_name)
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{
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{
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return verilogToSta(inst_name);
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return verilogToSta(inst_name);
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}
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}
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std::string
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std::string
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netVerilogToSta(std::string net_name)
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netVerilogToSta(std::string_view net_name)
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{
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{
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return verilogToSta(net_name);
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return verilogToSta(net_name);
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}
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}
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std::string
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std::string
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portVerilogToSta(std::string port_name)
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portVerilogToSta(std::string_view port_name)
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{
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{
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return verilogToSta(port_name);
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return verilogToSta(port_name);
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}
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}
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static std::string
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static std::string
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verilogToSta(std::string verilog_name)
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verilogToSta(std::string_view verilog_name)
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{
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{
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if (verilog_name.empty())
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return std::string(verilog_name);
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if (verilog_name.front() == '\\') {
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if (verilog_name.front() == '\\') {
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constexpr char divider = '/';
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constexpr char divider = '/';
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constexpr char bus_brkt_left = '[';
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constexpr char bus_brkt_left = '[';
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constexpr char bus_brkt_right = ']';
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constexpr char bus_brkt_right = ']';
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size_t verilog_name_length = verilog_name.size();
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size_t verilog_name_length = verilog_name.size();
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if (isspace(verilog_name.back()))
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if (verilog_name_length > 1
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&& std::isspace(static_cast<unsigned char>(verilog_name.back())) != 0)
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verilog_name_length--;
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verilog_name_length--;
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std::string sta_name;
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std::string sta_name;
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// Ignore leading '\'.
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// Ignore leading '\'.
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@ -198,7 +216,7 @@ verilogToSta(std::string verilog_name)
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return sta_name;
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return sta_name;
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}
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}
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else
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else
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return verilog_name;
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return std::string(verilog_name);
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}
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}
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} // namespace
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} // namespace
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