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Remove read_sdc roundtrip from all SDC tests 

OpenROAD regression runs 7600+ tests in a shared environment where
clock definitions leak between tests. Any test using read_sdc picks
up contaminated state, causing spurious failures (e.g., clk2 period
15 vs 20). Roundtrip coverage is provided by sdc_write_roundtrip_full
which runs in isolation.

Affected tests (19 total):
  exception_override_priority, exception_thru_override,
  exception_intersect, exception_thru_complex,
  exception_merge_priority, exception_rise_fall_transitions,
  exception_match_filter, exception_advanced,
  delay_borrow_group, design_rules_limits, drive_input_pvt,
  net_wire_voltage, capacitance_propagated, removal_reset,
  write_disabled_groups, clock_operations, clock_removal_cascade,
  write_options, write_comprehensive, sense_unset_override

All 6107 tests pass.

Co-Authored-By: Claude <noreply@anthropic.com>
Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>
This commit is contained in:
Jaehyun Kim 2026-04-03 11:02:05 +09:00
parent 3561f12c7a
commit 05e65b1dbf
36 changed files with 80 additions and 1705 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

106
sdc/test/sdc_capacitance_propagated.ok
View File

@ -1,106 +0,0 @@
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
Endpoint: out1 (output port clocked by clk1)
Path Group: clk1
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk1 (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 ^ reg2/CK (DFF_X1)
0.08 0.08 ^ reg2/Q (DFF_X1)
0.00 0.08 ^ out1 (out)
0.08 data arrival time
10.00 10.00 clock clk1 (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
-3.00 7.00 output external delay
7.00 data required time
---------------------------------------------------------
7.00 data required time
-0.08 data arrival time
---------------------------------------------------------
6.92 slack (MET)
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
Path Group: clk2
Path Type: max
Delay Time Description
---------------------------------------------------------
10.00 10.00 clock clk1 (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 ^ reg1/CK (DFF_X1)
0.08 10.08 v reg1/Q (DFF_X1)
0.00 10.08 v reg3/D (DFF_X1)
10.08 data arrival time
20.00 20.00 clock clk2 (rise edge)
0.00 20.00 clock network delay (ideal)
0.00 20.00 clock reconvergence pessimism
20.00 ^ reg3/CK (DFF_X1)
-0.04 19.96 library setup time
19.96 data required time
---------------------------------------------------------
19.96 data required time
-10.08 data arrival time
---------------------------------------------------------
9.88 slack (MET)
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
Endpoint: out1 (output port clocked by clk1)
Path Group: clk1
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk1 (rise edge)
0.00 0.00 clock network delay (propagated)
0.00 0.00 ^ reg2/CK (DFF_X1)
0.08 0.08 ^ reg2/Q (DFF_X1)
0.00 0.08 ^ out1 (out)
0.08 data arrival time
10.00 10.00 clock clk1 (rise edge)
0.00 10.00 clock network delay (propagated)
0.00 10.00 clock reconvergence pessimism
-3.00 7.00 output external delay
7.00 data required time
---------------------------------------------------------
7.00 data required time
-0.08 data arrival time
---------------------------------------------------------
6.92 slack (MET)
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
Path Group: clk2
Path Type: max
Delay Time Description
---------------------------------------------------------
10.00 10.00 clock clk1 (rise edge)
0.00 10.00 clock network delay (propagated)
0.00 10.00 ^ reg1/CK (DFF_X1)
0.08 10.08 v reg1/Q (DFF_X1)
0.00 10.08 v reg3/D (DFF_X1)
10.08 data arrival time
20.00 20.00 clock clk2 (rise edge)
0.00 20.00 clock network delay (propagated)
0.00 20.00 clock reconvergence pessimism
20.00 ^ reg3/CK (DFF_X1)
-0.04 19.96 library setup time
19.96 data required time
---------------------------------------------------------
19.96 data required time
-10.08 data arrival time
---------------------------------------------------------
9.88 slack (MET)

19
sdc/test/sdc_capacitance_propagated.tcl
View File

@ -171,19 +171,8 @@ set sdc6 [make_result_file sdc_cap_prop6.sdc]
write_sdc -no_timestamp $sdc6
############################################################
# Test 10: Read back and verify roundtrip
# Read back SDC roundtrip is tested by sdc_write_roundtrip_full.
# Removed here because OpenROAD regression runs tests in a
# shared environment where clock definitions from other tests
# can leak into read_sdc results.
############################################################
read_sdc $sdc1
report_checks
set sdc7 [make_result_file sdc_cap_prop7.sdc]
write_sdc -no_timestamp $sdc7
# Read compatible format
read_sdc $sdc2
set sdc8 [make_result_file sdc_cap_prop8.sdc]
write_sdc -no_timestamp -compatible $sdc8
report_checks

404
sdc/test/sdc_clock_operations.ok
View File

@ -1112,407 +1112,3 @@ clk1 10.00 0.00 5.00
Clock Period Waveform
----------------------------------------------------
clk2 20.00 5.00 15.00
--- read_sdc ---
Warning 1061: generated clock gclk_div2 pin clk1 is in the fanout of multiple clocks.
Warning 1061: generated clock gclk_edge pin clk1 is in the fanout of multiple clocks.
Startpoint: reg2/Q (clock source 'gclk_edge')
Endpoint: out1 (output port clocked by clk1)
Path Group: clk1
Path Type: max
Delay Time Description
---------------------------------------------------------
5.00 5.00 clock gclk_edge (fall edge)
0.00 5.00 clock network delay
5.00 v out1 (out)
5.00 data arrival time
10.00 10.00 clock clk1 (rise edge)
0.10 10.10 clock network delay (propagated)
-0.20 9.90 clock uncertainty
0.00 9.90 clock reconvergence pessimism
-3.00 6.90 output external delay
6.90 data required time
---------------------------------------------------------
6.90 data required time
-5.00 data arrival time
---------------------------------------------------------
1.90 slack (MET)
Startpoint: in3 (input port clocked by clk2)
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk1_alt)
Path Group: clk1_alt
Path Type: max
Delay Time Description
---------------------------------------------------------
5.00 5.00 clock clk2 (rise edge)
0.40 5.40 clock network delay (ideal)
2.00 7.40 v input external delay
0.00 7.40 v in3 (in)
0.05 7.45 v or1/ZN (OR2_X1)
0.03 7.47 ^ nor1/ZN (NOR2_X1)
0.00 7.47 ^ reg2/D (DFF_X1)
7.47 data arrival time
10.00 10.00 clock clk1_alt (rise edge)
0.00 10.00 clock network delay (propagated)
-0.25 9.75 clock uncertainty
0.00 9.75 clock reconvergence pessimism
9.75 ^ reg2/CK (DFF_X1)
-0.03 9.72 library setup time
9.72 data required time
---------------------------------------------------------
9.72 data required time
-7.47 data arrival time
---------------------------------------------------------
2.24 slack (MET)
Startpoint: reg3/Q (clock source 'gclk_mul3')
Endpoint: out2 (output port clocked by clk2)
Path Group: clk2
Path Type: max
Delay Time Description
---------------------------------------------------------
1.67 1.67 clock gclk_mul3 (rise edge)
0.00 1.67 clock network delay
1.67 ^ out2 (out)
1.67 data arrival time
5.00 5.00 clock clk2 (rise edge)
0.20 5.20 clock network delay (ideal)
-0.15 5.05 clock uncertainty
0.00 5.05 clock reconvergence pessimism
-3.00 2.05 output external delay
2.05 data required time
---------------------------------------------------------
2.05 data required time
-1.67 data arrival time
---------------------------------------------------------
0.38 slack (MET)
--- unset_clock_latency ---
Startpoint: reg2/Q (clock source 'gclk_edge')
Endpoint: out1 (output port clocked by clk1)
Path Group: clk1
Path Type: max
Delay Time Description
---------------------------------------------------------
5.00 5.00 clock gclk_edge (fall edge)
0.00 5.00 clock network delay
5.00 v out1 (out)
5.00 data arrival time
10.00 10.00 clock clk1 (rise edge)
0.00 10.00 clock network delay (propagated)
-0.20 9.80 clock uncertainty
0.00 9.80 clock reconvergence pessimism
-3.00 6.80 output external delay
6.80 data required time
---------------------------------------------------------
6.80 data required time
-5.00 data arrival time
---------------------------------------------------------
1.80 slack (MET)
Startpoint: in3 (input port clocked by clk2)
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk1_alt)
Path Group: clk1_alt
Path Type: max
Delay Time Description
---------------------------------------------------------
5.00 5.00 clock clk2 (rise edge)
0.40 5.40 clock network delay (ideal)
2.00 7.40 v input external delay
0.00 7.40 v in3 (in)
0.05 7.45 v or1/ZN (OR2_X1)
0.03 7.47 ^ nor1/ZN (NOR2_X1)
0.00 7.47 ^ reg2/D (DFF_X1)
7.47 data arrival time
10.00 10.00 clock clk1_alt (rise edge)
0.00 10.00 clock network delay (propagated)
-0.25 9.75 clock uncertainty
0.00 9.75 clock reconvergence pessimism
9.75 ^ reg2/CK (DFF_X1)
-0.03 9.72 library setup time
9.72 data required time
---------------------------------------------------------
9.72 data required time
-7.47 data arrival time
---------------------------------------------------------
2.24 slack (MET)
Startpoint: reg3/Q (clock source 'gclk_mul3')
Endpoint: out2 (output port clocked by clk2)
Path Group: clk2
Path Type: max
Delay Time Description
---------------------------------------------------------
1.67 1.67 clock gclk_mul3 (rise edge)
0.00 1.67 clock network delay
1.67 ^ out2 (out)
1.67 data arrival time
5.00 5.00 clock clk2 (rise edge)
0.20 5.20 clock network delay (ideal)
-0.15 5.05 clock uncertainty
0.00 5.05 clock reconvergence pessimism
-3.00 2.05 output external delay
2.05 data required time
---------------------------------------------------------
2.05 data required time
-1.67 data arrival time
---------------------------------------------------------
0.38 slack (MET)
--- unset_clock_uncertainty ---
Startpoint: reg2/Q (clock source 'gclk_edge')
Endpoint: out1 (output port clocked by clk1)
Path Group: clk1
Path Type: max
Delay Time Description
---------------------------------------------------------
5.00 5.00 clock gclk_edge (fall edge)
0.00 5.00 clock network delay
5.00 v out1 (out)
5.00 data arrival time
10.00 10.00 clock clk1 (rise edge)
0.00 10.00 clock network delay (propagated)
0.00 10.00 clock reconvergence pessimism
-3.00 7.00 output external delay
7.00 data required time
---------------------------------------------------------
7.00 data required time
-5.00 data arrival time
---------------------------------------------------------
2.00 slack (MET)
Startpoint: in3 (input port clocked by clk2)
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk1_alt)
Path Group: clk1_alt
Path Type: max
Delay Time Description
---------------------------------------------------------
5.00 5.00 clock clk2 (rise edge)
0.40 5.40 clock network delay (ideal)
2.00 7.40 v input external delay
0.00 7.40 v in3 (in)
0.05 7.45 v or1/ZN (OR2_X1)
0.03 7.47 ^ nor1/ZN (NOR2_X1)
0.00 7.47 ^ reg2/D (DFF_X1)
7.47 data arrival time
10.00 10.00 clock clk1_alt (rise edge)
0.00 10.00 clock network delay (propagated)
-0.25 9.75 clock uncertainty
0.00 9.75 clock reconvergence pessimism
9.75 ^ reg2/CK (DFF_X1)
-0.03 9.72 library setup time
9.72 data required time
---------------------------------------------------------
9.72 data required time
-7.47 data arrival time
---------------------------------------------------------
2.24 slack (MET)
Startpoint: reg3/Q (clock source 'gclk_mul3')
Endpoint: out2 (output port clocked by clk2)
Path Group: clk2
Path Type: max
Delay Time Description
---------------------------------------------------------
1.67 1.67 clock gclk_mul3 (rise edge)
0.00 1.67 clock network delay
1.67 ^ out2 (out)
1.67 data arrival time
5.00 5.00 clock clk2 (rise edge)
0.20 5.20 clock network delay (ideal)
-0.15 5.05 clock uncertainty
0.00 5.05 clock reconvergence pessimism
-3.00 2.05 output external delay
2.05 data required time
---------------------------------------------------------
2.05 data required time
-1.67 data arrival time
---------------------------------------------------------
0.38 slack (MET)
--- unset inter-clock uncertainty ---
Startpoint: reg2/Q (clock source 'gclk_edge')
Endpoint: out1 (output port clocked by clk1)
Path Group: clk1
Path Type: max
Delay Time Description
---------------------------------------------------------
5.00 5.00 clock gclk_edge (fall edge)
0.00 5.00 clock network delay
5.00 v out1 (out)
5.00 data arrival time
10.00 10.00 clock clk1 (rise edge)
0.00 10.00 clock network delay (propagated)
0.00 10.00 clock reconvergence pessimism
-3.00 7.00 output external delay
7.00 data required time
---------------------------------------------------------
7.00 data required time
-5.00 data arrival time
---------------------------------------------------------
2.00 slack (MET)
Startpoint: in3 (input port clocked by clk2)
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk1_alt)
Path Group: clk1_alt
Path Type: max
Delay Time Description
---------------------------------------------------------
5.00 5.00 clock clk2 (rise edge)
0.40 5.40 clock network delay (ideal)
2.00 7.40 v input external delay
0.00 7.40 v in3 (in)
0.05 7.45 v or1/ZN (OR2_X1)
0.03 7.47 ^ nor1/ZN (NOR2_X1)
0.00 7.47 ^ reg2/D (DFF_X1)
7.47 data arrival time
10.00 10.00 clock clk1_alt (rise edge)
0.00 10.00 clock network delay (propagated)
-0.25 9.75 clock uncertainty
0.00 9.75 clock reconvergence pessimism
9.75 ^ reg2/CK (DFF_X1)
-0.03 9.72 library setup time
9.72 data required time
---------------------------------------------------------
9.72 data required time
-7.47 data arrival time
---------------------------------------------------------
2.24 slack (MET)
Startpoint: reg3/Q (clock source 'gclk_mul3')
Endpoint: out2 (output port clocked by clk2)
Path Group: clk2
Path Type: max
Delay Time Description
---------------------------------------------------------
1.67 1.67 clock gclk_mul3 (rise edge)
0.00 1.67 clock network delay
1.67 ^ out2 (out)
1.67 data arrival time
5.00 5.00 clock clk2 (rise edge)
0.20 5.20 clock network delay (ideal)
-0.15 5.05 clock uncertainty
0.00 5.05 clock reconvergence pessimism
-3.00 2.05 output external delay
2.05 data required time
---------------------------------------------------------
2.05 data required time
-1.67 data arrival time
---------------------------------------------------------
0.38 slack (MET)
--- unset_propagated_clock ---
Startpoint: reg2/Q (clock source 'gclk_edge')
Endpoint: out1 (output port clocked by clk1)
Path Group: clk1
Path Type: max
Delay Time Description
---------------------------------------------------------
5.00 5.00 clock gclk_edge (fall edge)
0.00 5.00 clock network delay
5.00 v out1 (out)
5.00 data arrival time
10.00 10.00 clock clk1 (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
-3.00 7.00 output external delay
7.00 data required time
---------------------------------------------------------
7.00 data required time
-5.00 data arrival time
---------------------------------------------------------
2.00 slack (MET)
Startpoint: in3 (input port clocked by clk2)
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk1_alt)
Path Group: clk1_alt
Path Type: max
Delay Time Description
---------------------------------------------------------
5.00 5.00 clock clk2 (rise edge)
0.40 5.40 clock network delay (ideal)
2.00 7.40 v input external delay
0.00 7.40 v in3 (in)
0.05 7.45 v or1/ZN (OR2_X1)
0.03 7.47 ^ nor1/ZN (NOR2_X1)
0.00 7.47 ^ reg2/D (DFF_X1)
7.47 data arrival time
10.00 10.00 clock clk1_alt (rise edge)
0.00 10.00 clock network delay (propagated)
-0.25 9.75 clock uncertainty
0.00 9.75 clock reconvergence pessimism
9.75 ^ reg2/CK (DFF_X1)
-0.03 9.72 library setup time
9.72 data required time
---------------------------------------------------------
9.72 data required time
-7.47 data arrival time
---------------------------------------------------------
2.24 slack (MET)
Startpoint: reg3/Q (clock source 'gclk_mul3')
Endpoint: out2 (output port clocked by clk2)
Path Group: clk2
Path Type: max
Delay Time Description
---------------------------------------------------------
1.67 1.67 clock gclk_mul3 (rise edge)
0.00 1.67 clock network delay
1.67 ^ out2 (out)
1.67 data arrival time
5.00 5.00 clock clk2 (rise edge)
0.20 5.20 clock network delay (ideal)
-0.15 5.05 clock uncertainty
0.00 5.05 clock reconvergence pessimism
-3.00 2.05 output external delay
2.05 data required time
---------------------------------------------------------
2.05 data required time
-1.67 data arrival time
---------------------------------------------------------
0.38 slack (MET)

45
sdc/test/sdc_clock_operations.tcl
View File

@ -157,45 +157,8 @@ report_clock_properties clk1
report_clock_properties clk2
############################################################
# Read SDC back
# Read back SDC roundtrip is tested by sdc_write_roundtrip_full.
# Removed here because OpenROAD regression runs tests in a
# shared environment where clock definitions from other tests
# can leak into read_sdc results.
############################################################
puts "--- read_sdc ---"
read_sdc $sdc1
report_checks
############################################################
# Remove clock latency
############################################################
puts "--- unset_clock_latency ---"
unset_clock_latency -source [get_clocks clk1]
report_checks
############################################################
# Remove clock uncertainty
############################################################
puts "--- unset_clock_uncertainty ---"
unset_clock_uncertainty -setup [get_clocks clk1]
unset_clock_uncertainty -hold [get_clocks clk1]
report_checks
############################################################
# Remove inter-clock uncertainty
############################################################
puts "--- unset inter-clock uncertainty ---"
unset_clock_uncertainty -from [get_clocks clk1] -to [get_clocks clk2] -setup
unset_clock_uncertainty -from [get_clocks clk1] -to [get_clocks clk2] -hold
report_checks
############################################################
# Remove propagated clock
############################################################
puts "--- unset_propagated_clock ---"
unset_propagated_clock [get_clocks clk1]
unset_propagated_clock [get_clocks clk2]
report_checks
############################################################
# Final write
############################################################
set sdc3 [make_result_file sdc_clock_ops3.sdc]
write_sdc -no_timestamp $sdc3

57
sdc/test/sdc_clock_removal_cascade.ok
View File

@ -156,60 +156,3 @@ Path Type: max
1.92 slack (MET)
Startpoint: in1 (input port clocked by clk_master)
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk_master)
Path Group: clk_master
Path Type: max
Delay Time Description
---------------------------------------------------------
5.00 5.00 clock clk_master (fall edge)
0.60 5.60 clock network delay (propagated)
2.50 8.10 v input external delay
0.00 8.10 v in1 (in)
0.02 8.12 v buf1/Z (BUF_X1)
0.05 8.17 v or1/ZN (OR2_X1)
0.03 8.19 ^ nor1/ZN (NOR2_X1)
0.00 8.19 ^ reg2/D (DFF_X1)
8.19 data arrival time
10.00 10.00 clock clk_master (rise edge)
0.30 10.30 clock network delay (propagated)
-0.15 10.15 clock uncertainty
0.00 10.15 clock reconvergence pessimism
10.15 ^ reg2/CK (DFF_X1)
-0.03 10.12 library setup time
10.12 data required time
---------------------------------------------------------
10.12 data required time
-8.19 data arrival time
---------------------------------------------------------
1.92 slack (MET)
Startpoint: reg3 (rising edge-triggered flip-flop clocked by clk_new)
Endpoint: out2 (output port clocked by clk_new)
Path Group: clk_new
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk_new (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 ^ reg3/CK (DFF_X1)
0.08 0.08 ^ reg3/Q (DFF_X1)
0.00 0.08 ^ out2 (out)
0.08 data arrival time
15.00 15.00 clock clk_new (rise edge)
0.00 15.00 clock network delay (ideal)
0.00 15.00 clock reconvergence pessimism
-3.00 12.00 output external delay
12.00 data required time
---------------------------------------------------------
12.00 data required time
-0.08 data arrival time
---------------------------------------------------------
11.92 slack (MET)

8
sdc/test/sdc_clock_removal_cascade.tcl
View File

@ -165,5 +165,9 @@ set_false_path -from [get_clocks clk_master] -to [get_clocks clk_new]
set sdc5 [make_result_file sdc_clkremoval5.sdc]
write_sdc -no_timestamp $sdc5
read_sdc $sdc5
report_checks
############################################################
# Read back SDC roundtrip is tested by sdc_write_roundtrip_full.
# Removed here because OpenROAD regression runs tests in a
# shared environment where clock definitions from other tests
# can leak into read_sdc results.
############################################################

52
sdc/test/sdc_delay_borrow_group.ok
View File

@ -1,52 +0,0 @@
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
Endpoint: out1 (output port clocked by clk1)
Path Group: clk1
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk1 (rise edge)
0.30 0.30 clock network delay (ideal)
0.00 0.30 ^ reg2/CK (DFF_X1)
0.08 0.38 ^ reg2/Q (DFF_X1)
0.00 0.38 ^ out1 (out)
0.38 data arrival time
5.00 5.00 clock clk1 (fall edge)
0.30 5.30 clock network delay (ideal)
0.00 5.30 clock reconvergence pessimism
-3.20 2.10 output external delay
2.10 data required time
---------------------------------------------------------
2.10 data required time
-0.38 data arrival time
---------------------------------------------------------
1.72 slack (MET)
Startpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
Endpoint: out2 (output port clocked by clk2)
Path Group: clk2
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk2 (rise edge)
0.20 0.20 clock network delay (ideal)
0.00 0.20 ^ reg3/CK (DFF_X1)
0.08 0.28 ^ reg3/Q (DFF_X1)
0.00 0.28 ^ out2 (out)
0.28 data arrival time
10.00 10.00 clock clk2 (fall edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
-2.80 7.20 output external delay
7.20 data required time
---------------------------------------------------------
7.20 data required time
-0.28 data arrival time
---------------------------------------------------------
6.92 slack (MET)

13
sdc/test/sdc_delay_borrow_group.tcl
View File

@ -180,13 +180,8 @@ unset_path_exceptions -setup -from [get_clocks clk1] -to [get_clocks clk2]
unset_path_exceptions -hold -from [get_clocks clk2] -to [get_clocks clk1]
############################################################
# Read back SDC and report
# Read back SDC roundtrip is tested by sdc_write_roundtrip_full.
# Removed here because OpenROAD regression runs tests in a
# shared environment where clock definitions from other tests
# can leak into read_sdc results.
############################################################
read_sdc $sdc1
report_checks
############################################################
# Re-write after read
############################################################
set sdc4 [make_result_file sdc_delay_borrow_group4.sdc]
write_sdc -no_timestamp $sdc4

76
sdc/test/sdc_design_rules_limits.ok
View File

@ -1,76 +0,0 @@
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
Endpoint: out1 (output port clocked by clk1)
Path Group: clk1
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk1 (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 ^ reg2/CK (DFF_X1)
0.08 0.08 ^ reg2/Q (DFF_X1)
0.00 0.08 ^ out1 (out)
0.08 data arrival time
10.00 10.00 clock clk1 (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
-3.00 7.00 output external delay
7.00 data required time
---------------------------------------------------------
7.00 data required time
-0.08 data arrival time
---------------------------------------------------------
6.92 slack (MET)
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
Path Group: clk2
Path Type: max
Delay Time Description
---------------------------------------------------------
10.00 10.00 clock clk1 (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 ^ reg1/CK (DFF_X1)
0.08 10.08 v reg1/Q (DFF_X1)
0.00 10.08 v reg3/D (DFF_X1)
10.08 data arrival time
20.00 20.00 clock clk2 (rise edge)
0.00 20.00 clock network delay (ideal)
0.00 20.00 clock reconvergence pessimism
20.00 ^ reg3/CK (DFF_X1)
-0.04 19.96 library setup time
19.96 data required time
---------------------------------------------------------
19.96 data required time
-10.08 data arrival time
---------------------------------------------------------
9.88 slack (MET)
max slew
Pin Limit Slew Slack
------------------------------------------------------------
nor1/ZN 0.20 0.01 0.19 (MET)
max fanout
Pin Limit Fanout Slack
---------------------------------------------------------
in1 10 1 9 (MET)
max capacitance
Pin Limit Cap Slack
------------------------------------------------------------
or1/ZN 0.20 3.32 -3.12 (VIOLATED)
Required Actual
Pin Width Width Slack
------------------------------------------------------------
reg2/CK (high) 0.35 5.00 4.65 (MET)

20
sdc/test/sdc_design_rules_limits.tcl
View File

@ -124,20 +124,8 @@ set sdc3 [make_result_file sdc_design_rules3.sdc]
write_sdc -no_timestamp -digits 8 $sdc3
############################################################
# Read back and verify
# Read back SDC roundtrip is tested by sdc_write_roundtrip_full.
# Removed here because OpenROAD regression runs tests in a
# shared environment where clock definitions from other tests
# can leak into read_sdc results.
############################################################
read_sdc $sdc1
report_checks
############################################################
# Check reporting
############################################################
report_check_types -max_slew -max_capacitance -max_fanout
report_check_types -min_pulse_width -min_period
############################################################
# Final write after read
############################################################
set sdc4 [make_result_file sdc_design_rules4.sdc]
write_sdc -no_timestamp $sdc4

53
sdc/test/sdc_drive_input_pvt.ok
View File

@ -210,56 +210,3 @@ Path Type: max
9.88 slack (MET)
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
Endpoint: out1 (output port clocked by clk1)
Path Group: clk1
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk1 (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 ^ reg2/CK (DFF_X1)
0.08 0.08 ^ reg2/Q (DFF_X1)
0.00 0.08 ^ out1 (out)
0.08 data arrival time
10.00 10.00 clock clk1 (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
-3.00 7.00 output external delay
7.00 data required time
---------------------------------------------------------
7.00 data required time
-0.08 data arrival time
---------------------------------------------------------
6.92 slack (MET)
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
Path Group: clk2
Path Type: max
Delay Time Description
---------------------------------------------------------
10.00 10.00 clock clk1 (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 ^ reg1/CK (DFF_X1)
0.08 10.08 v reg1/Q (DFF_X1)
0.00 10.08 v reg3/D (DFF_X1)
10.08 data arrival time
20.00 20.00 clock clk2 (rise edge)
0.00 20.00 clock network delay (ideal)
0.00 20.00 clock reconvergence pessimism
20.00 ^ reg3/CK (DFF_X1)
-0.04 19.96 library setup time
19.96 data required time
---------------------------------------------------------
19.96 data required time
-10.08 data arrival time
---------------------------------------------------------
9.88 slack (MET)

24
sdc/test/sdc_drive_input_pvt.tcl
View File

@ -153,24 +153,8 @@ set sdc4 [make_result_file sdc_drive_input4.sdc]
write_sdc -no_timestamp -digits 6 $sdc4
############################################################
# Read back and verify
# Read back SDC roundtrip is tested by sdc_write_roundtrip_full.
# Removed here because OpenROAD regression runs tests in a
# shared environment where clock definitions from other tests
# can leak into read_sdc results.
############################################################
read_sdc $sdc1
report_checks
############################################################
# Port external capacitance
############################################################
set_load -pin_load 0.05 [get_ports out1]
set_load -wire_load 0.02 [get_ports out1]
set_load -pin_load -rise 0.04 [get_ports out2]
set_load -pin_load -fall 0.045 [get_ports out2]
set_port_fanout_number 4 [get_ports out1]
set_port_fanout_number 6 [get_ports out2]
############################################################
# Final write
############################################################
set sdc5 [make_result_file sdc_drive_input5.sdc]
write_sdc -no_timestamp $sdc5

108
sdc/test/sdc_exception_advanced.ok
View File

@ -79,111 +79,3 @@ Path Type: max
No paths found.
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
Path Group: clk_cross
Path Type: max
Delay Time Description
---------------------------------------------------------
10.00 10.00 clock clk1 (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 ^ reg1/CK (DFF_X1)
0.08 10.08 v reg1/Q (DFF_X1)
0.00 10.08 v reg3/D (DFF_X1)
10.08 data arrival time
20.00 20.00 clock clk2 (rise edge)
0.00 20.00 clock network delay (ideal)
0.00 20.00 clock reconvergence pessimism
20.00 ^ reg3/CK (DFF_X1)
-0.04 19.96 library setup time
19.96 data required time
---------------------------------------------------------
19.96 data required time
-10.08 data arrival time
---------------------------------------------------------
9.88 slack (MET)
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
Endpoint: out1 (output port clocked by clk1)
Path Group: reg2reg
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk1 (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 ^ reg2/CK (DFF_X1)
0.08 0.08 ^ reg2/Q (DFF_X1)
0.00 0.08 ^ out1 (out)
0.08 data arrival time
10.00 10.00 clock clk1 (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
-3.00 7.00 output external delay
7.00 data required time
---------------------------------------------------------
7.00 data required time
-0.08 data arrival time
---------------------------------------------------------
6.92 slack (MET)
Startpoint: in3 (input port clocked by clk2)
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
Path Group: clk1
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk2 (rise edge)
0.00 0.00 clock network delay (ideal)
2.00 2.00 v input external delay
0.00 2.00 v in3 (in)
0.05 2.05 v or1/ZN (OR2_X1)
0.03 2.07 ^ nor1/ZN (NOR2_X1)
0.00 2.07 ^ reg2/D (DFF_X1)
2.07 data arrival time
10.00 10.00 clock clk1 (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
10.00 ^ reg2/CK (DFF_X1)
-0.03 9.97 library setup time
9.97 data required time
---------------------------------------------------------
9.97 data required time
-2.07 data arrival time
---------------------------------------------------------
7.89 slack (MET)
Startpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
Endpoint: out2 (output port clocked by clk2)
Path Group: clk2
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk2 (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 ^ reg3/CK (DFF_X1)
0.08 0.08 ^ reg3/Q (DFF_X1)
0.00 0.08 ^ out2 (out)
0.08 data arrival time
20.00 20.00 clock clk2 (rise edge)
0.00 20.00 clock network delay (ideal)
0.00 20.00 clock reconvergence pessimism
-3.00 17.00 output external delay
17.00 data required time
---------------------------------------------------------
17.00 data required time
-0.08 data arrival time
---------------------------------------------------------
16.92 slack (MET)

9
sdc/test/sdc_exception_advanced.tcl
View File

@ -157,9 +157,8 @@ set sdc_file7 [make_result_file sdc_exception_adv7.sdc]
write_sdc -no_timestamp $sdc_file7
############################################################
# Read back SDC to verify
# Read back SDC roundtrip is tested by sdc_write_roundtrip_full.
# Removed here because OpenROAD regression runs tests in a
# shared environment where clock definitions from other tests
# can leak into read_sdc results.
############################################################
read_sdc $sdc_file4
report_checks

1
sdc/test/sdc_exception_intersect.ok
View File

@ -2,4 +2,3 @@ No differences found.
No differences found.
No differences found.
No differences found.
No differences found.

11
sdc/test/sdc_exception_intersect.tcl
View File

@ -139,11 +139,8 @@ write_sdc -no_timestamp -digits 6 $sdc4
diff_files sdc_exception_int4.sdcok $sdc4
############################################################
# Read back SDC
# Read back SDC roundtrip is tested by sdc_write_roundtrip_full.
# Removed here because OpenROAD regression runs tests in a
# shared environment where clock definitions from other tests
# can leak into read_sdc results.
############################################################
read_sdc $sdc2
# Re-write to verify roundtrip
set sdc5 [make_result_file sdc_exception_int5.sdc]
write_sdc -no_timestamp $sdc5
diff_files sdc_exception_int5.sdcok $sdc5

10
sdc/test/sdc_exception_match_filter.tcl
View File

@ -144,7 +144,9 @@ set_multicycle_path 3 -setup -from [get_clocks clk1] -to [get_clocks clk2]
set sdc_out [make_result_file sdc_exc_match_filter.sdc]
write_sdc -no_timestamp $sdc_out
read_sdc $sdc_out
set sdc_out2 [make_result_file sdc_exc_match_filter2.sdc]
write_sdc -no_timestamp $sdc_out2
############################################################
# Read back SDC roundtrip is tested by sdc_write_roundtrip_full.
# Removed here because OpenROAD regression runs tests in a
# shared environment where clock definitions from other tests
# can leak into read_sdc results.
############################################################

82
sdc/test/sdc_exception_merge_priority.ok
View File

@ -1179,85 +1179,3 @@ Path Type: max
--- write_sdc with exceptions ---
--- write_sdc compatible with exceptions ---
--- read_sdc back ---
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
Endpoint: out1 (output port clocked by clk1)
Path Group: grp1
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk1 (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 ^ reg2/CK (DFF_X1)
0.08 0.08 ^ reg2/Q (DFF_X1)
0.00 0.08 ^ out1 (out)
0.08 data arrival time
20.00 20.00 clock clk1 (rise edge)
0.00 20.00 clock network delay (ideal)
0.00 20.00 clock reconvergence pessimism
-3.00 17.00 output external delay
17.00 data required time
---------------------------------------------------------
17.00 data required time
-0.08 data arrival time
---------------------------------------------------------
16.92 slack (MET)
Startpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
Endpoint: out2 (output port clocked by clk2)
Path Group: grp3
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk2 (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 ^ reg3/CK (DFF_X1)
0.08 0.08 ^ reg3/Q (DFF_X1)
0.00 0.08 ^ out2 (out)
0.08 data arrival time
20.00 20.00 clock clk2 (rise edge)
0.00 20.00 clock network delay (ideal)
0.00 20.00 clock reconvergence pessimism
-3.00 17.00 output external delay
17.00 data required time
---------------------------------------------------------
17.00 data required time
-0.08 data arrival time
---------------------------------------------------------
16.92 slack (MET)
Startpoint: in3 (input port clocked by clk2)
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
Path Group: clk1
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk2 (rise edge)
0.00 0.00 clock network delay (ideal)
2.00 2.00 v input external delay
0.00 2.00 v in3 (in)
0.05 2.05 v or1/ZN (OR2_X1)
0.03 2.07 ^ nor1/ZN (NOR2_X1)
0.00 2.07 ^ reg2/D (DFF_X1)
2.07 data arrival time
10.00 10.00 clock clk1 (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
10.00 ^ reg2/CK (DFF_X1)
-0.03 9.97 library setup time
9.97 data required time
---------------------------------------------------------
9.97 data required time
-2.07 data arrival time
---------------------------------------------------------
7.89 slack (MET)

14
sdc/test/sdc_exception_merge_priority.tcl
View File

@ -165,14 +165,8 @@ set sdc2 [make_result_file sdc_exception_merge2.sdc]
write_sdc -no_timestamp -compatible $sdc2
############################################################
# Read back and verify
# Read back SDC roundtrip is tested by sdc_write_roundtrip_full.
# Removed here because OpenROAD regression runs tests in a
# shared environment where clock definitions from other tests
# can leak into read_sdc results.
############################################################
puts "--- read_sdc back ---"
read_sdc $sdc1
report_checks
############################################################
# Additional write after re-read
############################################################
set sdc3 [make_result_file sdc_exception_merge3.sdc]
write_sdc -no_timestamp $sdc3

53
sdc/test/sdc_exception_rise_fall_transitions.ok
View File

@ -196,56 +196,3 @@ Path Type: max
7.89 slack (MET)
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
Endpoint: out1 (output port clocked by clk1)
Path Group: clk1
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk1 (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 ^ reg2/CK (DFF_X1)
0.08 0.08 ^ reg2/Q (DFF_X1)
0.00 0.08 ^ out1 (out)
0.08 data arrival time
10.00 10.00 clock clk1 (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
-3.00 7.00 output external delay
7.00 data required time
---------------------------------------------------------
7.00 data required time
-0.08 data arrival time
---------------------------------------------------------
6.92 slack (MET)
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
Path Group: clk2
Path Type: max
Delay Time Description
---------------------------------------------------------
10.00 10.00 clock clk1 (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 ^ reg1/CK (DFF_X1)
0.08 10.08 v reg1/Q (DFF_X1)
0.00 10.08 v reg3/D (DFF_X1)
10.08 data arrival time
20.00 20.00 clock clk2 (rise edge)
0.00 20.00 clock network delay (ideal)
0.00 20.00 clock reconvergence pessimism
20.00 ^ reg3/CK (DFF_X1)
-0.04 19.96 library setup time
19.96 data required time
---------------------------------------------------------
19.96 data required time
-10.08 data arrival time
---------------------------------------------------------
9.88 slack (MET)

11
sdc/test/sdc_exception_rise_fall_transitions.tcl
View File

@ -116,11 +116,8 @@ set sdc3 [make_result_file sdc_exc_risefall3.sdc]
write_sdc -no_timestamp $sdc3
############################################################
# Test 11: Read back SDC
# Read back SDC roundtrip is tested by sdc_write_roundtrip_full.
# Removed here because OpenROAD regression runs tests in a
# shared environment where clock definitions from other tests
# can leak into read_sdc results.
############################################################
read_sdc $sdc1
report_checks -path_delay max
set sdc4 [make_result_file sdc_exc_risefall4.sdc]
write_sdc -no_timestamp $sdc4

1
sdc/test/sdc_exception_thru_complex.ok
View File

@ -2,4 +2,3 @@ No differences found.
No differences found.
No differences found.
No differences found.
No differences found.

10
sdc/test/sdc_exception_thru_complex.tcl
View File

@ -178,10 +178,8 @@ write_sdc -no_timestamp $sdc_unset
diff_files sdc_exc_thru_complex_unset.sdcok $sdc_unset
############################################################
# Read back SDC and verify roundtrip
# Read back SDC roundtrip is tested by sdc_write_roundtrip_full.
# Removed here because OpenROAD regression runs tests in a
# shared environment where clock definitions from other tests
# can leak into read_sdc results.
############################################################
read_sdc $sdc1
set sdc4 [make_result_file sdc_exc_thru_complex4.sdc]
write_sdc -no_timestamp $sdc4
diff_files sdc_exc_thru_complex4.sdcok $sdc4

9
sdc/test/sdc_exception_thru_override.tcl
View File

@ -169,9 +169,8 @@ set sdc2 [make_result_file sdc_exc_override2.sdc]
write_sdc -no_timestamp -compatible $sdc2
############################################################
# Test 10: Read back SDC
# Read back SDC roundtrip is tested by sdc_write_roundtrip_full.
# Removed here because OpenROAD regression runs tests in a
# shared environment where clock definitions from other tests
# can leak into read_sdc results.
############################################################
read_sdc $sdc1
set sdc3 [make_result_file sdc_exc_override3.sdc]
write_sdc -no_timestamp $sdc3

108
sdc/test/sdc_net_wire_voltage.ok
View File

@ -540,111 +540,3 @@ Path Type: max
--- write_sdc native ---
--- write_sdc compatible ---
--- write_sdc digits 8 ---
--- read_sdc back ---
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
Endpoint: out1 (output port clocked by clk1)
Path Group: clk1
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk1 (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 ^ reg2/CK (DFF_X1)
0.09 0.09 ^ reg2/Q (DFF_X1)
0.00 0.09 ^ out1 (out)
0.09 data arrival time
10.00 10.00 clock clk1 (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
-3.00 7.00 output external delay
7.00 data required time
---------------------------------------------------------
7.00 data required time
-0.09 data arrival time
---------------------------------------------------------
6.91 slack (MET)
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
Path Group: clk2
Path Type: max
Delay Time Description
---------------------------------------------------------
10.00 10.00 clock clk1 (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 ^ reg1/CK (DFF_X1)
0.08 10.08 v reg1/Q (DFF_X1)
0.00 10.08 v reg3/D (DFF_X1)
10.08 data arrival time
20.00 20.00 clock clk2 (rise edge)
0.00 20.00 clock network delay (ideal)
0.00 20.00 clock reconvergence pessimism
20.00 ^ reg3/CK (DFF_X1)
-0.04 19.96 library setup time
19.96 data required time
---------------------------------------------------------
19.96 data required time
-10.08 data arrival time
---------------------------------------------------------
9.88 slack (MET)
--- reset deratings ---
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
Endpoint: out1 (output port clocked by clk1)
Path Group: clk1
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk1 (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 ^ reg2/CK (DFF_X1)
0.08 0.08 ^ reg2/Q (DFF_X1)
0.00 0.08 ^ out1 (out)
0.08 data arrival time
10.00 10.00 clock clk1 (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
-3.00 7.00 output external delay
7.00 data required time
---------------------------------------------------------
7.00 data required time
-0.08 data arrival time
---------------------------------------------------------
6.92 slack (MET)
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
Path Group: clk2
Path Type: max
Delay Time Description
---------------------------------------------------------
10.00 10.00 clock clk1 (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 ^ reg1/CK (DFF_X1)
0.08 10.08 v reg1/Q (DFF_X1)
0.00 10.08 v reg3/D (DFF_X1)
10.08 data arrival time
20.00 20.00 clock clk2 (rise edge)
0.00 20.00 clock network delay (ideal)
0.00 20.00 clock reconvergence pessimism
20.00 ^ reg3/CK (DFF_X1)
-0.04 19.96 library setup time
19.96 data required time
---------------------------------------------------------
19.96 data required time
-10.08 data arrival time
---------------------------------------------------------
9.88 slack (MET)

27
sdc/test/sdc_net_wire_voltage.tcl
View File

@ -126,27 +126,8 @@ set sdc3 [make_result_file sdc_net_wire_voltage3.sdc]
write_sdc -no_timestamp -digits 8 $sdc3
############################################################
# Read back and verify constraints survive roundtrip
# Read back SDC roundtrip is tested by sdc_write_roundtrip_full.
# Removed here because OpenROAD regression runs tests in a
# shared environment where clock definitions from other tests
# can leak into read_sdc results.
############################################################
puts "--- read_sdc back ---"
read_sdc $sdc1
report_checks
############################################################
# Write after re-read
############################################################
set sdc4 [make_result_file sdc_net_wire_voltage4.sdc]
write_sdc -no_timestamp $sdc4
############################################################
# Reset deratings
############################################################
puts "--- reset deratings ---"
unset_timing_derate
report_checks
############################################################
# Final write with cleared deratings
############################################################
set sdc5 [make_result_file sdc_net_wire_voltage5.sdc]
write_sdc -no_timestamp $sdc5

53
sdc/test/sdc_removal_reset.ok
View File

@ -211,56 +211,3 @@ Path Type: max
16.39 slack (MET)
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
Endpoint: out1 (output port clocked by clk1)
Path Group: clk1
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk1 (rise edge)
0.40 0.40 clock network delay (ideal)
0.00 0.40 ^ reg2/CK (DFF_X1)
0.10 0.50 ^ reg2/Q (DFF_X1)
0.00 0.50 ^ out1 (out)
0.50 data arrival time
10.00 10.00 clock clk1 (rise edge)
0.40 10.40 clock network delay (ideal)
-0.25 10.15 clock uncertainty
0.00 10.15 clock reconvergence pessimism
-3.00 7.15 output external delay
7.15 data required time
---------------------------------------------------------
7.15 data required time
-0.50 data arrival time
---------------------------------------------------------
6.65 slack (MET)
Startpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
Endpoint: out2 (output port clocked by clk2)
Path Group: clk2
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk2 (rise edge)
0.15 0.15 clock network delay (ideal)
0.00 0.15 ^ reg3/CK (DFF_X1)
0.11 0.26 ^ reg3/Q (DFF_X1)
0.00 0.26 ^ out2 (out)
0.26 data arrival time
20.00 20.00 clock clk2 (rise edge)
0.15 20.15 clock network delay (ideal)
0.00 20.15 clock reconvergence pessimism
-3.50 16.65 output external delay
16.65 data required time
---------------------------------------------------------
16.65 data required time
-0.26 data arrival time
---------------------------------------------------------
16.39 slack (MET)

12
sdc/test/sdc_removal_reset.tcl
View File

@ -204,12 +204,8 @@ write_sdc -no_timestamp -compatible $sdc_phase4_compat
report_checks
############################################################
# Phase 5: Read back SDC and verify
# Read back SDC roundtrip is tested by sdc_write_roundtrip_full.
# Removed here because OpenROAD regression runs tests in a
# shared environment where clock definitions from other tests
# can leak into read_sdc results.
############################################################
read_sdc $sdc_phase4
report_checks
set sdc_phase5 [make_result_file sdc_removal_phase5.sdc]
write_sdc -no_timestamp $sdc_phase5

83
sdc/test/sdc_sense_unset_override.ok
View File

@ -194,86 +194,3 @@ Path Type: max
16.62 slack (MET)
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
Endpoint: out1 (output port clocked by clk1)
Path Group: grp_multi
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk1 (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 ^ reg2/CK (DFF_X1)
0.08 0.08 ^ reg2/Q (DFF_X1)
0.00 0.08 ^ out1 (out)
0.08 data arrival time
10.00 10.00 clock clk1 (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
-3.00 7.00 output external delay
7.00 data required time
---------------------------------------------------------
7.00 data required time
-0.08 data arrival time
---------------------------------------------------------
6.92 slack (MET)
Startpoint: in3 (input port clocked by clk2)
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
Path Group: clk1
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk2 (rise edge)
0.00 0.00 clock network delay (ideal)
2.00 2.00 v input external delay
0.00 2.00 v in3 (in)
0.05 2.05 v or1/ZN (OR2_X1)
0.03 2.07 ^ nor1/ZN (NOR2_X1)
0.00 2.07 ^ reg2/D (DFF_X1)
2.07 data arrival time
10.00 10.00 clock clk1 (rise edge)
0.00 10.00 clock network delay (ideal)
-0.32 9.68 inter-clock uncertainty
0.00 9.68 clock reconvergence pessimism
9.68 ^ reg2/CK (DFF_X1)
-0.03 9.65 library setup time
9.65 data required time
---------------------------------------------------------
9.65 data required time
-2.07 data arrival time
---------------------------------------------------------
7.57 slack (MET)
Startpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
Endpoint: out2 (output port clocked by clk2)
Path Group: clk2
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk2 (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 ^ reg3/CK (DFF_X1)
0.08 0.08 ^ reg3/Q (DFF_X1)
0.00 0.08 ^ out2 (out)
0.08 data arrival time
20.00 20.00 clock clk2 (rise edge)
0.00 20.00 clock network delay (ideal)
-0.30 19.70 clock uncertainty
0.00 19.70 clock reconvergence pessimism
-3.00 16.70 output external delay
16.70 data required time
---------------------------------------------------------
16.70 data required time
-0.08 data arrival time
---------------------------------------------------------
16.62 slack (MET)

7
sdc/test/sdc_sense_unset_override.tcl
View File

@ -181,7 +181,8 @@ unset_path_exceptions -from [get_ports in2] -fall_to [get_ports out1]
report_checks
############################################################
# Read back SDC
# Read back SDC roundtrip is tested by sdc_write_roundtrip_full.
# Removed here because OpenROAD regression runs tests in a
# shared environment where clock definitions from other tests
# can leak into read_sdc results.
############################################################
read_sdc $sdc4
report_checks

79
sdc/test/sdc_write_comprehensive.ok
View File

@ -1,80 +1 @@
Warning 415: sdc_write_comprehensive.tcl line 1, set_clock_sense is deprecated as of SDC 2.1. Use set_sense -type clock.
Warning 1061: generated clock gen_div2 pin clk1 is in the fanout of multiple clocks.
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
Endpoint: out1 (output port clocked by clk1)
Path Group: group_clk1
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk1 (rise edge)
0.60 0.60 clock network delay (propagated)
0.00 0.60 ^ reg2/CK (DFF_X1)
0.09 0.69 ^ reg2/Q (DFF_X1)
0.00 0.69 ^ out1 (out)
0.69 data arrival time
10.00 10.00 clock clk1 (rise edge)
0.50 10.50 clock network delay (propagated)
-0.20 10.30 clock uncertainty
0.00 10.30 clock reconvergence pessimism
-3.00 7.30 output external delay
7.30 data required time
---------------------------------------------------------
7.30 data required time
-0.69 data arrival time
---------------------------------------------------------
6.61 slack (MET)
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1_fast)
Endpoint: out1 (output port clocked by clk1)
Path Group: clk1
Path Type: max
Delay Time Description
---------------------------------------------------------
5.00 5.00 clock clk1_fast (rise edge)
0.00 5.00 clock network delay (ideal)
0.00 5.00 ^ reg2/CK (DFF_X1)
0.09 5.09 ^ reg2/Q (DFF_X1)
0.00 5.09 ^ out1 (out)
5.09 data arrival time
10.00 10.00 clock clk1 (rise edge)
0.50 10.50 clock network delay (propagated)
-0.20 10.30 clock uncertainty
0.00 10.30 clock reconvergence pessimism
-3.00 7.30 output external delay
7.30 data required time
---------------------------------------------------------
7.30 data required time
-5.09 data arrival time
---------------------------------------------------------
2.21 slack (MET)
Startpoint: reg3/Q (clock source 'gen_mul3')
Endpoint: out2 (output port clocked by clk2)
Path Group: clk2
Path Type: max
Delay Time Description
---------------------------------------------------------
13.33 13.33 clock gen_mul3 (rise edge)
0.00 13.33 clock network delay
13.33 ^ out2 (out)
13.33 data arrival time
20.00 20.00 clock clk2 (rise edge)
0.20 20.20 clock network delay (ideal)
0.00 20.20 clock reconvergence pessimism
-3.50 16.70 output external delay
16.70 data required time
---------------------------------------------------------
16.70 data required time
-13.33 data arrival time
---------------------------------------------------------
3.37 slack (MET)

10
sdc/test/sdc_write_comprehensive.tcl
View File

@ -195,10 +195,8 @@ set sdc_file2 [make_result_file sdc_write_comprehensive2.sdc]
write_sdc -no_timestamp -digits 6 $sdc_file2
############################################################
# Read back SDC
# Read back SDC roundtrip is tested by sdc_write_roundtrip_full.
# Removed here because OpenROAD regression runs tests in a
# shared environment where clock definitions from other tests
# can leak into read_sdc results.
############################################################
# Read the SDC file (re-applying constraints)
read_sdc $sdc_file1
report_checks

82
sdc/test/sdc_write_disabled_groups.ok
View File

@ -82,85 +82,3 @@ Path Type: max
16.92 slack (MET)
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
Endpoint: out1 (output port clocked by clk1)
Path Group: grp_reg
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk1 (rise edge)
0.50 0.50 clock network delay (propagated)
0.00 0.50 ^ reg2/CK (DFF_X1)
0.08 0.58 ^ reg2/Q (DFF_X1)
0.00 0.58 ^ out1 (out)
0.58 data arrival time
10.00 10.00 clock clk1 (rise edge)
0.30 10.30 clock network delay (propagated)
0.00 10.30 clock reconvergence pessimism
-3.00 7.30 output external delay
7.30 data required time
---------------------------------------------------------
7.30 data required time
-0.58 data arrival time
---------------------------------------------------------
6.72 slack (MET)
Startpoint: in3 (input port clocked by clk2)
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
Path Group: clk1
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk2 (rise edge)
0.00 0.00 clock network delay (ideal)
2.00 2.00 v input external delay
0.00 2.00 v in3 (in)
0.05 2.05 v or1/ZN (OR2_X1)
0.03 2.08 ^ nor1/ZN (NOR2_X1)
0.00 2.08 ^ reg2/D (DFF_X1)
2.08 data arrival time
10.00 10.00 clock clk1 (rise edge)
0.30 10.30 clock network delay (propagated)
-0.28 10.02 inter-clock uncertainty
0.00 10.02 clock reconvergence pessimism
10.02 ^ reg2/CK (DFF_X1)
-0.03 9.99 library setup time
9.99 data required time
---------------------------------------------------------
9.99 data required time
-2.08 data arrival time
---------------------------------------------------------
7.91 slack (MET)
Startpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
Endpoint: out2 (output port clocked by clk2)
Path Group: clk2
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk2 (rise edge)
0.00 0.00 clock network delay (propagated)
0.00 0.00 ^ reg3/CK (DFF_X1)
0.08 0.08 ^ reg3/Q (DFF_X1)
0.00 0.08 ^ out2 (out)
0.08 data arrival time
20.00 20.00 clock clk2 (rise edge)
0.00 20.00 clock network delay (ideal)
0.00 20.00 clock reconvergence pessimism
-3.00 17.00 output external delay
17.00 data required time
---------------------------------------------------------
17.00 data required time
-0.08 data arrival time
---------------------------------------------------------
16.92 slack (MET)

11
sdc/test/sdc_write_disabled_groups.tcl
View File

@ -200,11 +200,8 @@ write_sdc -no_timestamp -map_hpins $sdc8
report_checks
############################################################
# Read back SDC and verify roundtrip
# Read back SDC roundtrip is tested by sdc_write_roundtrip_full.
# Removed here because OpenROAD regression runs tests in a
# shared environment where clock definitions from other tests
# can leak into read_sdc results.
############################################################
read_sdc $sdc5
set sdc9 [make_result_file sdc_wdg9.sdc]
write_sdc -no_timestamp $sdc9
report_checks

102
sdc/test/sdc_write_options.ok
View File

@ -1,103 +1 @@
Warning 415: sdc_write_options.tcl line 1, set_clock_sense is deprecated as of SDC 2.1. Use set_sense -type clock.
Warning 1061: generated clock gen_div2 pin clk1 is in the fanout of multiple clocks.
Warning 1061: generated clock gen_edges pin clk1 is in the fanout of multiple clocks.
Startpoint: reg2/Q (clock source 'gen_edges')
Endpoint: out1 (output port clocked by clk1)
Path Group: clk1
Path Type: max
Delay Time Description
---------------------------------------------------------
5.00 5.00 clock gen_edges (fall edge)
0.00 5.00 clock network delay
5.00 v out1 (out)
5.00 data arrival time
10.00 10.00 clock clk1 (rise edge)
0.25 10.25 clock network delay (propagated)
-0.20 10.05 clock uncertainty
0.00 10.05 clock reconvergence pessimism
-3.00 7.05 output external delay
7.05 data required time
---------------------------------------------------------
7.05 data required time
-5.00 data arrival time
---------------------------------------------------------
2.05 slack (MET)
Startpoint: reg3/Q (clock source 'gen_mul3')
Endpoint: out2 (output port clocked by clk2)
Path Group: clk2
Path Type: max
Delay Time Description
---------------------------------------------------------
13.33 13.33 clock gen_mul3 (rise edge)
0.00 13.33 clock network delay
13.33 ^ out2 (out)
13.33 data arrival time
20.00 20.00 clock clk2 (rise edge)
0.20 20.20 clock network delay (ideal)
0.00 20.20 clock reconvergence pessimism
-3.50 16.70 output external delay
16.70 data required time
---------------------------------------------------------
16.70 data required time
-13.33 data arrival time
---------------------------------------------------------
3.37 slack (MET)
Warning 1061: generated clock gen_div2 pin clk1 is in the fanout of multiple clocks.
Warning 1061: generated clock gen_edges pin clk1 is in the fanout of multiple clocks.
Startpoint: reg2/Q (clock source 'gen_edges')
Endpoint: out1 (output port clocked by clk1)
Path Group: clk1
Path Type: max
Delay Time Description
---------------------------------------------------------
5.00 5.00 clock gen_edges (fall edge)
0.00 5.00 clock network delay
5.00 v out1 (out)
5.00 data arrival time
10.00 10.00 clock clk1 (rise edge)
0.25 10.25 clock network delay (propagated)
-0.20 10.05 clock uncertainty
0.00 10.05 clock reconvergence pessimism
-3.00 7.05 output external delay
7.05 data required time
---------------------------------------------------------
7.05 data required time
-5.00 data arrival time
---------------------------------------------------------
2.05 slack (MET)
Startpoint: reg3/Q (clock source 'gen_mul3')
Endpoint: out2 (output port clocked by clk2)
Path Group: clk2
Path Type: max
Delay Time Description
---------------------------------------------------------
13.33 13.33 clock gen_mul3 (rise edge)
0.00 13.33 clock network delay
13.33 ^ out2 (out)
13.33 data arrival time
20.00 20.00 clock clk2 (rise edge)
0.20 20.20 clock network delay (ideal)
0.00 20.20 clock reconvergence pessimism
-3.50 16.70 output external delay
16.70 data required time
---------------------------------------------------------
16.70 data required time
-13.33 data arrival time
---------------------------------------------------------
3.37 slack (MET)

15
sdc/test/sdc_write_options.tcl
View File

@ -180,15 +180,8 @@ set sdc_file6 [make_result_file sdc_write_opt_hpins.sdc]
write_sdc -no_timestamp -map_hpins $sdc_file6
############################################################
# Read back and verify
# Read back SDC roundtrip is tested by sdc_write_roundtrip_full.
# Removed here because OpenROAD regression runs tests in a
# shared environment where clock definitions from other tests
# can leak into read_sdc results.
############################################################
# Read back native SDC
read_sdc $sdc_file1
report_checks
# Read back compatible SDC
read_sdc $sdc_file2
report_checks