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OpenSTA
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Merge remote-tracking branch 'parallax/master' 

Signed-off-by: Matt Liberty <mliberty@precisioninno.com>
This commit is contained in:
Matt Liberty 2024-04-29 08:46:15 -07:00
parent f8a9e1771b fdca0dff7a
commit 00c2082003
8 changed files with 64 additions and 57 deletions
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16
include/sta/Sdc.hh
View File

@ -239,8 +239,8 @@ public:
const RiseFall *rf, const RiseFall *rf,
const EarlyLate *early_late) const; const EarlyLate *early_late) const;
void unsetTimingDerate(); void unsetTimingDerate();
static void moveDeratingFactors(Sdc *from, static void swapDeratingFactors(Sdc *sdc1,
Sdc *to); Sdc *sdc2);
void setInputSlew(const Port *port, void setInputSlew(const Port *port,
const RiseFallBoth *rf, const RiseFallBoth *rf,
@ -445,8 +445,8 @@ public:
float delay); float delay);
void removeClockInsertion(const Clock *clk, void removeClockInsertion(const Clock *clk,
const Pin *pin); const Pin *pin);
static void moveClockInsertions(Sdc *from, static void swapClockInsertions(Sdc *sdc1,
Sdc *to); Sdc *sdc2);
bool hasClockInsertion(const Pin *pin) const; bool hasClockInsertion(const Pin *pin) const;
float clockInsertion(const Clock *clk, float clockInsertion(const Clock *clk,
const RiseFall *rf, const RiseFall *rf,
@ -569,8 +569,8 @@ public:
const Clock *clk, const Clock *clk,
const RiseFall *clk_rf, const RiseFall *clk_rf,
const MinMaxAll *min_max); const MinMaxAll *min_max);
static void movePortDelays(Sdc *from, static void swapPortDelays(Sdc *sdc1,
Sdc *to); Sdc *sdc2);
// Set port external pin load (set_load -pin_load port). // Set port external pin load (set_load -pin_load port).
void setPortExtPinCap(const Port *port, void setPortExtPinCap(const Port *port,
@ -585,8 +585,8 @@ public:
const Corner *corner, const Corner *corner,
const MinMax *min_max, const MinMax *min_max,
float cap); float cap);
static void movePortExtCaps(Sdc *from, static void swapPortExtCaps(Sdc *sdc1,
Sdc *to); Sdc *sdc2);
// Remove all "set_load net" annotations. // Remove all "set_load net" annotations.
void removeNetLoadCaps(); void removeNetLoadCaps();
void setNetWireCap(const Net *net, void setNetWireCap(const Net *net,

62
sdc/Sdc.cc
View File

@ -51,6 +51,8 @@
namespace sta { namespace sta {
using std::swap;
bool bool
ClockPairLess::operator()(const ClockPair &pair1, ClockPairLess::operator()(const ClockPair &pair1,
const ClockPair &pair2) const const ClockPair &pair2) const
@ -660,17 +662,13 @@ Sdc::unsetTimingDerate()
} }
void void
Sdc::moveDeratingFactors(Sdc *from, Sdc::swapDeratingFactors(Sdc *sdc1,
Sdc *to) Sdc *sdc2)
{ {
if (from->derating_factors_) { swap(sdc1->derating_factors_, sdc2->derating_factors_);
to->derating_factors_ = from->derating_factors_; swap(sdc1->net_derating_factors_, sdc2->net_derating_factors_);
from->derating_factors_ = nullptr; swap(sdc1->inst_derating_factors_, sdc2->inst_derating_factors_);
} swap(sdc1->cell_derating_factors_, sdc2->cell_derating_factors_);
to->net_derating_factors_ = std::move(from->net_derating_factors_);
to->inst_derating_factors_ = std::move(from->inst_derating_factors_);
to->cell_derating_factors_ = std::move(from->cell_derating_factors_);
} }
void void
@ -1733,10 +1731,10 @@ Sdc::removeClockInsertion(const Clock *clk,
} }
void void
Sdc::moveClockInsertions(Sdc *from, Sdc::swapClockInsertions(Sdc *sdc1,
Sdc *to) Sdc *sdc2)
{ {
to->clk_insertions_ = std::move(from->clk_insertions_); swap(sdc1->clk_insertions_, sdc2->clk_insertions_);
} }
void void
@ -2742,21 +2740,20 @@ Sdc::deleteInputDelay(InputDelay *input_delay)
} }
void void
Sdc::movePortDelays(Sdc *from, Sdc::swapPortDelays(Sdc *sdc1,
Sdc *to) Sdc *sdc2)
{ {
to->input_delays_ = std::move(from->input_delays_); swap(sdc1->input_delays_, sdc2->input_delays_);
to->input_delay_pin_map_ = std::move(from->input_delay_pin_map_); swap(sdc1->input_delay_pin_map_, sdc2->input_delay_pin_map_);
to->input_delay_ref_pin_map_ = std::move(from->input_delay_ref_pin_map_); swap(sdc1->input_delay_ref_pin_map_, sdc2->input_delay_ref_pin_map_);
to->input_delay_leaf_pin_map_ = std::move(from->input_delay_leaf_pin_map_); swap(sdc1->input_delay_leaf_pin_map_, sdc2->input_delay_leaf_pin_map_);
to->input_delay_internal_pin_map_ = std::move(from->input_delay_internal_pin_map_); swap(sdc1->input_delay_internal_pin_map_, sdc2->input_delay_internal_pin_map_);
to->input_delay_index_ = from->input_delay_index_; swap(sdc1->input_delay_index_, sdc2->input_delay_index_);
from->input_delay_index_ = 0;
to->output_delays_ = std::move(from->output_delays_); swap(sdc1->output_delays_, sdc2->output_delays_);
to->output_delay_pin_map_ = std::move(from->output_delay_pin_map_); swap(sdc1->output_delay_pin_map_, sdc2->output_delay_pin_map_);
to->output_delay_ref_pin_map_ = std::move(from->output_delay_ref_pin_map_); swap(sdc1->output_delay_ref_pin_map_, sdc2->output_delay_ref_pin_map_);
to->output_delay_leaf_pin_map_ = std::move(from->output_delay_leaf_pin_map_); swap(sdc1->output_delay_leaf_pin_map_, sdc2->output_delay_leaf_pin_map_);
} }
//////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////
@ -3322,15 +3319,12 @@ Sdc::ensurePortExtPinCap(const Port *port,
} }
void void
Sdc::movePortExtCaps(Sdc *from, Sdc::swapPortExtCaps(Sdc *sdc1,
Sdc *to) Sdc *sdc2)
{ {
for (int corner_index = 0; corner_index < from->corners()->count(); corner_index++) { for (int corner_index = 0; corner_index < sdc1->corners()->count(); corner_index++) {
to->port_ext_cap_maps_[corner_index] = swap(sdc1->port_ext_cap_maps_[corner_index], sdc2->port_ext_cap_maps_[corner_index]);
std::move(from->port_ext_cap_maps_[corner_index]); swap(sdc1->net_wire_cap_maps_[corner_index], sdc2->net_wire_cap_maps_[corner_index]);
to->net_wire_cap_maps_[corner_index] =
std::move(from->net_wire_cap_maps_[corner_index]);
} }
} }

19
search/MakeTimingModel.cc
View File

@ -111,24 +111,27 @@ void
MakeTimingModel::saveSdc() MakeTimingModel::saveSdc()
{ {
sdc_backup_ = new Sdc(this); sdc_backup_ = new Sdc(this);
Sdc::movePortDelays(sdc_, sdc_backup_); swapSdcWithBackup();
Sdc::movePortExtCaps(sdc_, sdc_backup_);
Sdc::moveDeratingFactors(sdc_, sdc_backup_);
Sdc::moveClockInsertions(sdc_, sdc_backup_);
sta_->delaysInvalid(); sta_->delaysInvalid();
} }
void void
MakeTimingModel::restoreSdc() MakeTimingModel::restoreSdc()
{ {
Sdc::movePortDelays(sdc_backup_, sdc_); swapSdcWithBackup();
Sdc::movePortExtCaps(sdc_backup_, sdc_);
Sdc::moveDeratingFactors(sdc_backup_, sdc_);
Sdc::moveClockInsertions(sdc_backup_, sdc_);
delete sdc_backup_; delete sdc_backup_;
sta_->delaysInvalid(); sta_->delaysInvalid();
} }
void
MakeTimingModel::swapSdcWithBackup()
{
Sdc::swapPortDelays(sdc_, sdc_backup_);
Sdc::swapPortExtCaps(sdc_, sdc_backup_);
Sdc::swapDeratingFactors(sdc_, sdc_backup_);
Sdc::swapClockInsertions(sdc_, sdc_backup_);
}
void void
MakeTimingModel::makeLibrary() MakeTimingModel::makeLibrary()
{ {

1
search/MakeTimingModelPvt.hh
View File

@ -92,6 +92,7 @@ private:
void saveSdc(); void saveSdc();
void restoreSdc(); void restoreSdc();
void swapSdcWithBackup();
const char *lib_name_; const char *lib_name_;
const char *cell_name_; const char *cell_name_;

2
search/Sta.cc
View File

@ -2968,7 +2968,7 @@ Sta::netSlack(const Net *net,
{ {
ensureGraph(); ensureGraph();
Slack slack = MinMax::min()->initValue(); Slack slack = MinMax::min()->initValue();
NetPinIterator *pin_iter = network_->pinIterator(net); NetConnectedPinIterator *pin_iter = network_->connectedPinIterator(net);
while (pin_iter->hasNext()) { while (pin_iter->hasNext()) {
const Pin *pin = pin_iter->next(); const Pin *pin = pin_iter->next();
if (network_->isLoad(pin)) { if (network_->isLoad(pin)) {

9
verilog/VerilogParse.yy
View File

@ -505,9 +505,14 @@ attr_specs:
attr_spec: attr_spec:
ID ID
{ $$ = new sta::VerilogAttributeEntry($1, "1"); } { $$ = new sta::VerilogAttributeEntry($1, "1");
delete[] $1;
}
| ID '=' attr_spec_value | ID '=' attr_spec_value
{ $$ = new sta::VerilogAttributeEntry($1, $3); } { $$ = new sta::VerilogAttributeEntry($1, $3);
delete[] $1;
delete[] $3;
}
; ;
attr_spec_value: attr_spec_value:

5
verilog/VerilogReader.cc
View File

@ -424,8 +424,11 @@ VerilogReader::makeDcl(PortDirection *dir,
dcl_count_++; dcl_count_++;
return new VerilogDcl(dir, assign_args, attribute_stmts, line); return new VerilogDcl(dir, assign_args, attribute_stmts, line);
} }
else else {
attribute_stmts->deleteContents();
delete attribute_stmts;
return nullptr; return nullptr;
}
} }
else { else {
dcl_count_++; dcl_count_++;

7
verilog/VerilogWriter.cc
View File

@ -214,9 +214,9 @@ VerilogWriter::verilogPortDir(PortDirection *dir)
else if (dir == PortDirection::bidirect()) else if (dir == PortDirection::bidirect())
return "inout"; return "inout";
else if (dir == PortDirection::power()) else if (dir == PortDirection::power())
return "input"; return "inout";
else if (dir == PortDirection::ground()) else if (dir == PortDirection::ground())
return "input"; return "inout";
else if (dir == PortDirection::internal()) else if (dir == PortDirection::internal())
return nullptr; return nullptr;
else { else {
@ -412,7 +412,8 @@ VerilogWriter::writeAssigns(Instance *inst)
Net *net = network_->net(term); Net *net = network_->net(term);
Port *port = network_->port(pin); Port *port = network_->port(pin);
if (port if (port
&& network_->direction(port)->isAnyOutput() && (network_->direction(port)->isAnyOutput()
|| network_->direction(port)->isPowerGround())
&& !stringEqual(network_->name(port), network_->name(net))) { && !stringEqual(network_->name(port), network_->name(net))) {
// Port name is different from net name. // Port name is different from net name.
string port_vname = netVerilogName(network_->name(port), string port_vname = netVerilogName(network_->name(port),