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OpenSTA/test/verilog_unconnected_hpin.ok

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Fix for OpenSTA issue 398 and OpenROAD issue 9454 with regression (#401) * Fix for OpenSTA issue 398 and OpenROAD issue 9454 with regression Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com> * Incorporated feedbacks from previous version Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com> * rename tests Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com> * remove unnecessary newline Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com> * Updated to use network_->portBitIterator Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com> --------- Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>
2026-03-10 22:57:21 +01:00
Find b1/out2: b1/out2
Find b2/out2: b2/out2
Net b2/out2
Pin capacitance: 0.00
Wire capacitance: 0.00
Total capacitance: 0.00
Number of drivers: 1
Number of loads: 0
Number of pins: 1
Driver pins
b2/u3/Y output (BUFx2_ASAP7_75t_R)