277 lines
10 KiB
C++
277 lines
10 KiB
C++
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// OpenSTA, Static Timing Analyzer
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// Copyright (c) 2022, Parallax Software, Inc.
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <https://www.gnu.org/licenses/>.
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#include "MakeTimingModel.hh"
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#include "Debug.hh"
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#include "Units.hh"
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#include "Transition.hh"
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#include "Liberty.hh"
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#include "liberty/LibertyBuilder.hh"
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#include "LibertyWriter.hh"
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#include "Network.hh"
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#include "PortDirection.hh"
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#include "Corner.hh"
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#include "DcalcAnalysisPt.hh"
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#include "dcalc/GraphDelayCalc1.hh"
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#include "Sdc.hh"
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#include "StaState.hh"
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#include "Sta.hh"
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namespace sta {
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void
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writeTimingModel(const char *cell_name,
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const char *filename,
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const Corner *corner,
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Sta *sta)
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{
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MakeTimingModel writer(corner, sta);
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writer.writeTimingModel(cell_name, filename);
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}
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MakeTimingModel::MakeTimingModel(const Corner *corner,
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Sta *sta) :
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StaState(sta),
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sta_(sta),
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corner_(corner),
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min_max_(MinMax::max()),
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lib_builder_(new LibertyBuilder)
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{
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}
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MakeTimingModel::~MakeTimingModel()
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{
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delete lib_builder_;
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}
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void
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MakeTimingModel::writeTimingModel(const char *cell_name,
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const char *filename)
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{
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makeTimingModel(cell_name, filename);
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writeLibertyFile(filename);
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}
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void
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MakeTimingModel::writeLibertyFile(const char *filename)
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{
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writeLiberty(library_, filename, this);
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}
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void
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MakeTimingModel::makeTimingModel(const char *cell_name,
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const char *filename)
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{
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makeLibrary(cell_name, filename);
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makeCell(cell_name, filename);
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makePorts();
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for (Clock *clk : *sdc_->clocks())
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sta_->setPropagatedClock(clk);
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#if 0
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findInputToOutputPaths();
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findInputSetupHolds();
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findClkedOutputPaths();
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#endif
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findInputSetupHolds();
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}
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void
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MakeTimingModel::makeLibrary(const char *cell_name,
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const char *filename)
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{
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library_ = network_->makeLibertyLibrary(cell_name, filename);
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LibertyLibrary *default_lib = network_->defaultLibertyLibrary();
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*library_->units()->timeUnit() = *default_lib->units()->timeUnit();
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*library_->units()->capacitanceUnit() = *default_lib->units()->capacitanceUnit();
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*library_->units()->voltageUnit() = *default_lib->units()->voltageUnit();
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*library_->units()->resistanceUnit() = *default_lib->units()->resistanceUnit();
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*library_->units()->pullingResistanceUnit() = *default_lib->units()->pullingResistanceUnit();
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*library_->units()->powerUnit() = *default_lib->units()->powerUnit();
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*library_->units()->distanceUnit() = *default_lib->units()->distanceUnit();
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for (RiseFall *rf : RiseFall::range()) {
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library_->setInputThreshold(rf, default_lib->inputThreshold(rf));
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library_->setOutputThreshold(rf, default_lib->outputThreshold(rf));
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library_->setSlewLowerThreshold(rf, default_lib->slewLowerThreshold(rf));
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library_->setSlewUpperThreshold(rf, default_lib->slewUpperThreshold(rf));
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}
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library_->setDelayModelType(default_lib->delayModelType());
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library_->setNominalProcess(default_lib->nominalProcess());
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library_->setNominalVoltage(default_lib->nominalVoltage());
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library_->setNominalTemperature(default_lib->nominalTemperature());
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}
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void
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MakeTimingModel::makeCell(const char *cell_name,
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const char *filename)
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{
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cell_ = lib_builder_->makeCell(library_, cell_name, filename);
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}
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void
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MakeTimingModel::makePorts()
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{
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const DcalcAnalysisPt *dcalc_ap = corner_->findDcalcAnalysisPt(min_max_);
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InstancePinIterator *pin_iter = network_->pinIterator(network_->topInstance());
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while (pin_iter->hasNext()) {
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Pin *pin = pin_iter->next();
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Port *port = network_->port(pin);
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LibertyPort *lib_port = lib_builder_->makePort(cell_, network_->name(port));
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lib_port->setDirection(network_->direction(port));
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float load_cap = graph_delay_calc_->loadCap(pin, dcalc_ap);
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lib_port->setCapacitance(load_cap);
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}
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delete pin_iter;
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}
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// input -> output combinational paths
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void
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MakeTimingModel::findInputToOutputPaths()
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{
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InstancePinIterator *input_iter = network_->pinIterator(network_->topInstance());
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while (input_iter->hasNext()) {
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Pin *input_pin = input_iter->next();
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if (network_->direction(input_pin)->isInput()
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&& !sta_->isClockSrc(input_pin)) {
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InstancePinIterator *output_iter = network_->pinIterator(network_->topInstance());
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while (output_iter->hasNext()) {
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Pin *output_pin = output_iter->next();
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if (network_->direction(output_pin)->isOutput()) {
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PinSet *from_pins = new PinSet;
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from_pins->insert(input_pin);
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ExceptionFrom *from = sta_->makeExceptionFrom(from_pins, nullptr, nullptr,
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RiseFallBoth::riseFall());
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PinSet *to_pins = new PinSet;
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to_pins->insert(output_pin);
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ExceptionTo *to = sta_->makeExceptionTo(to_pins, nullptr, nullptr,
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RiseFallBoth::riseFall(),
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RiseFallBoth::riseFall());
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PathEndSeq *ends = sta_->findPathEnds(from, nullptr, to, true, corner_,
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min_max_->asMinMaxAll(),
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1, 1, false,
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-INF, INF, false, nullptr,
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false, false, false, false, false, false);
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if (!ends->empty()) {
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debugPrint(debug_, "timing_model", 1, "input %s -> output %s",
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network_->pathName(input_pin),
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network_->pathName(output_pin));
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PathEnd *end = (*ends)[0];
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sta_->reportPathEnd(end);
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}
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}
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}
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}
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}
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}
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// input -> register setup/hold
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void
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MakeTimingModel::findInputSetupHolds()
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{
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InstancePinIterator *input_iter = network_->pinIterator(network_->topInstance());
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while (input_iter->hasNext()) {
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Pin *input_pin = input_iter->next();
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if (network_->direction(input_pin)->isInput()
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&& !sta_->isClockSrc(input_pin)) {
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for (Clock *clk : *sdc_->clocks()) {
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for (RiseFall *clk_rf : RiseFall::range()) {
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for (MinMax *min_max : MinMax::range()) {
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MinMaxAll *min_max2 = min_max->asMinMaxAll();
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bool setup = min_max == MinMax::max();
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bool hold = !setup;
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for (RiseFall *input_rf : RiseFall::range()) {
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sdc_->setInputDelay(input_pin, RiseFallBoth::riseFall(), clk, clk_rf,
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nullptr, false, false, min_max2, false, 0.0);
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PinSet *from_pins = new PinSet;
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from_pins->insert(input_pin);
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ExceptionFrom *from = sta_->makeExceptionFrom(from_pins, nullptr, nullptr,
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input_rf->asRiseFallBoth());
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ClockSet *to_clks = new ClockSet;
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to_clks->insert(clk);
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ExceptionTo *to = sta_->makeExceptionTo(nullptr, to_clks, nullptr,
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clk_rf->asRiseFallBoth(),
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RiseFallBoth::riseFall());
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PathEndSeq *ends = sta_->findPathEnds(from, nullptr, to, false, corner_,
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min_max2,
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1, 1, false,
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-INF, INF, false, nullptr,
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setup, hold, setup, hold, setup, hold);
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if (!ends->empty()) {
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debugPrint(debug_, "timing_model", 1, "%s %s %s -> clock %s %s",
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setup ? "setup" : "hold",
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network_->pathName(input_pin),
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input_rf->asString(),
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clk->name(),
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clk_rf->asString());
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PathEnd *end = (*ends)[0];
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sta_->reportPathEnd(end);
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}
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}
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}
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}
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}
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}
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}
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}
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void
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MakeTimingModel::findClkedOutputPaths()
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{
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InstancePinIterator *output_iter = network_->pinIterator(network_->topInstance());
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while (output_iter->hasNext()) {
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Pin *output_pin = output_iter->next();
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if (network_->direction(output_pin)->isOutput()) {
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for (Clock *clk : *sdc_->clocks()) {
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for (RiseFall *clk_rf : RiseFall::range()) {
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sdc_->setOutputDelay(output_pin, RiseFallBoth::riseFall(), clk, clk_rf,
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nullptr, false, false, MinMaxAll::max(), false, 0.0);
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ClockSet *from_clks = new ClockSet;
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from_clks->insert(clk);
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ExceptionFrom *from = sta_->makeExceptionFrom(nullptr, from_clks, nullptr,
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clk_rf->asRiseFallBoth());
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PinSet *to_pins = new PinSet;
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to_pins->insert(output_pin);
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ExceptionTo *to = sta_->makeExceptionTo(to_pins, nullptr, nullptr,
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RiseFallBoth::riseFall(),
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RiseFallBoth::riseFall());
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PathEndSeq *ends = sta_->findPathEnds(from, nullptr, to, false, corner_,
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MinMaxAll::max(),
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1, 1, false,
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-INF, INF, false, nullptr,
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true, false, false, false, false, false);
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if (!ends->empty()) {
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debugPrint(debug_, "timing_model", 1, "clock %s -> output %s",
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clk->name(),
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network_->pathName(output_pin));
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PathEnd *end = (*ends)[0];
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sta_->reportPathEnd(end);
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}
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}
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}
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}
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}
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}
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} // namespace
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