209 lines
7.1 KiB
Plaintext
209 lines
7.1 KiB
Plaintext
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Startpoint: r2 (rising edge-triggered flip-flop clocked by m1_clk)
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Endpoint: r3 (rising edge-triggered flip-flop clocked by m1_clk)
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Path Group: m1_clk
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Path Type: max
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Mode: mode1
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Corner: scene1
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock m1_clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
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52.65 52.65 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
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49.30 101.95 ^ u1/Y (BUFx2_ASAP7_75t_R)
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61.03 162.97 ^ u2/Y (AND2x2_ASAP7_75t_R)
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15.77 178.74 ^ r3/D (DFFHQx4_ASAP7_75t_R)
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178.74 data arrival time
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1000.00 1000.00 clock m1_clk (rise edge)
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0.00 1000.00 clock network delay (ideal)
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0.00 1000.00 clock reconvergence pessimism
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1000.00 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
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-13.66 986.34 library setup time
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986.34 data required time
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---------------------------------------------------------
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986.34 data required time
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-178.74 data arrival time
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---------------------------------------------------------
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807.59 slack (MET)
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Startpoint: r1 (rising edge-triggered flip-flop clocked by m2_clk)
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Endpoint: r3 (rising edge-triggered flip-flop clocked by m2_clk)
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Path Group: m2_clk
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Path Type: max
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Mode: mode2
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Corner: scene2
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock m2_clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ r1/CLK (DFFHQx4_ASAP7_75t_R)
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123.56 123.56 ^ r1/Q (DFFHQx4_ASAP7_75t_R)
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112.01 235.57 ^ u2/Y (AND2x2_ASAP7_75t_R)
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22.14 257.71 ^ r3/D (DFFHQx4_ASAP7_75t_R)
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257.71 data arrival time
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500.00 500.00 clock m2_clk (rise edge)
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0.00 500.00 clock network delay (ideal)
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0.00 500.00 clock reconvergence pessimism
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500.00 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
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-40.66 459.34 library setup time
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459.34 data required time
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---------------------------------------------------------
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459.34 data required time
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-257.71 data arrival time
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---------------------------------------------------------
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201.62 slack (MET)
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Startpoint: r2 (rising edge-triggered flip-flop clocked by m1_clk)
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Endpoint: r3 (rising edge-triggered flip-flop clocked by m1_clk)
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Path Group: m1_clk
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Path Type: max
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Mode: mode1
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Corner: scene1
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock m1_clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
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52.65 52.65 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
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49.30 101.95 ^ u1/Y (BUFx2_ASAP7_75t_R)
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61.03 162.97 ^ u2/Y (AND2x2_ASAP7_75t_R)
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15.77 178.74 ^ r3/D (DFFHQx4_ASAP7_75t_R)
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178.74 data arrival time
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1000.00 1000.00 clock m1_clk (rise edge)
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0.00 1000.00 clock network delay (ideal)
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0.00 1000.00 clock reconvergence pessimism
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1000.00 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
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-13.66 986.34 library setup time
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986.34 data required time
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---------------------------------------------------------
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986.34 data required time
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-178.74 data arrival time
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---------------------------------------------------------
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807.59 slack (MET)
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Startpoint: in1 (input port clocked by m1_clk)
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Endpoint: r1 (rising edge-triggered flip-flop clocked by m1_clk)
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Path Group: m1_clk
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Path Type: max
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Mode: mode1
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Corner: scene1
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock m1_clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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100.00 100.00 ^ input external delay
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0.00 100.00 ^ in1 (in)
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12.28 112.28 ^ r1/D (DFFHQx4_ASAP7_75t_R)
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112.28 data arrival time
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1000.00 1000.00 clock m1_clk (rise edge)
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0.00 1000.00 clock network delay (ideal)
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0.00 1000.00 clock reconvergence pessimism
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1000.00 ^ r1/CLK (DFFHQx4_ASAP7_75t_R)
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-12.80 987.20 library setup time
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987.20 data required time
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---------------------------------------------------------
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987.20 data required time
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-112.28 data arrival time
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---------------------------------------------------------
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874.92 slack (MET)
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Startpoint: in2 (input port clocked by m1_clk)
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Endpoint: r2 (rising edge-triggered flip-flop clocked by m1_clk)
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Path Group: m1_clk
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Path Type: max
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Mode: mode1
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Corner: scene1
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock m1_clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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100.00 100.00 ^ input external delay
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0.00 100.00 ^ in2 (in)
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12.28 112.28 ^ r2/D (DFFHQx4_ASAP7_75t_R)
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112.28 data arrival time
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1000.00 1000.00 clock m1_clk (rise edge)
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0.00 1000.00 clock network delay (ideal)
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0.00 1000.00 clock reconvergence pessimism
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1000.00 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
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-12.80 987.20 library setup time
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987.20 data required time
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---------------------------------------------------------
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987.20 data required time
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-112.28 data arrival time
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---------------------------------------------------------
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874.92 slack (MET)
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Startpoint: r1 (rising edge-triggered flip-flop clocked by m2_clk)
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Endpoint: r3 (rising edge-triggered flip-flop clocked by m2_clk)
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Path Group: m2_clk
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Path Type: max
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Mode: mode2
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Corner: scene2
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock m2_clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ r1/CLK (DFFHQx4_ASAP7_75t_R)
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123.56 123.56 ^ r1/Q (DFFHQx4_ASAP7_75t_R)
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112.01 235.57 ^ u2/Y (AND2x2_ASAP7_75t_R)
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22.14 257.71 ^ r3/D (DFFHQx4_ASAP7_75t_R)
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257.71 data arrival time
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500.00 500.00 clock m2_clk (rise edge)
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0.00 500.00 clock network delay (ideal)
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0.00 500.00 clock reconvergence pessimism
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500.00 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
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-40.66 459.34 library setup time
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459.34 data required time
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---------------------------------------------------------
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459.34 data required time
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-257.71 data arrival time
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---------------------------------------------------------
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201.62 slack (MET)
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Startpoint: r3 (rising edge-triggered flip-flop clocked by m2_clk)
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Endpoint: out (output port clocked by m2_clk)
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Path Group: m2_clk
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Path Type: max
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Mode: mode2
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Corner: scene2
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock m2_clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
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123.30 123.30 ^ r3/Q (DFFHQx4_ASAP7_75t_R)
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19.50 142.80 ^ out (out)
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142.80 data arrival time
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500.00 500.00 clock m2_clk (rise edge)
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0.00 500.00 clock network delay (ideal)
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0.00 500.00 clock reconvergence pessimism
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-100.00 400.00 output external delay
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400.00 data required time
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---------------------------------------------------------
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400.00 data required time
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-142.80 data arrival time
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---------------------------------------------------------
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257.20 slack (MET)
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