Add {`instance`, `cell`, `verilog_src`, `pin`, `net`, `hier_pins`, `capacitance`} fields to `report_checks -format json` for paths (#135)
* Add {`inst`, `cell`, `src`, `nets`} to `report_checks -format json`
* Smallfix
* Improved nets
* Race condition fix
* Fixes
* Small whitespace fix
* Add no paths corner case stuff
* Adjustments to naming of fields
* Requested fixes
* Reintroduce escapeBackslashes, use stringCopy to prevent stack memory warning
* Fix escapeBackslashes to use preferred style
* No backslash escaping
* Make requested fixes
2025-01-14 04:28:04 +01:00
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{"checks": [
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{
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"type": "check",
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"path_group": "clk",
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"path_type": "max",
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"startpoint": "_1415_/Q",
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"endpoint": "_1416_[0]/D",
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"source_clock": "clk",
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"source_clock_edge": "rise",
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2025-08-13 18:53:44 +02:00
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"source_clock_path": [
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Add {`instance`, `cell`, `verilog_src`, `pin`, `net`, `hier_pins`, `capacitance`} fields to `report_checks -format json` for paths (#135)
* Add {`inst`, `cell`, `src`, `nets`} to `report_checks -format json`
* Smallfix
* Improved nets
* Race condition fix
* Fixes
* Small whitespace fix
* Add no paths corner case stuff
* Adjustments to naming of fields
* Requested fixes
* Reintroduce escapeBackslashes, use stringCopy to prevent stack memory warning
* Fix escapeBackslashes to use preferred style
* No backslash escaping
* Make requested fixes
2025-01-14 04:28:04 +01:00
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{
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"instance": "",
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"cell": "counter",
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"verilog_src": "",
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"pin": "clk",
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"arrival": 0.000e+00,
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"capacitance": 3.742e-15,
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"slew": 0.000e+00
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},
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{
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"instance": "_1415_",
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"cell": "sky130_fd_sc_hd__dfrtp_1",
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"verilog_src": "synthesis/tests/counter.v:22.3-28.6",
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"pin": "_1415_/CLK",
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"net": "clk",
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"arrival": 0.000e+00,
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"slew": 0.000e+00
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2025-08-13 18:53:44 +02:00
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}
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],
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"source_path": [
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Add {`instance`, `cell`, `verilog_src`, `pin`, `net`, `hier_pins`, `capacitance`} fields to `report_checks -format json` for paths (#135)
* Add {`inst`, `cell`, `src`, `nets`} to `report_checks -format json`
* Smallfix
* Improved nets
* Race condition fix
* Fixes
* Small whitespace fix
* Add no paths corner case stuff
* Adjustments to naming of fields
* Requested fixes
* Reintroduce escapeBackslashes, use stringCopy to prevent stack memory warning
* Fix escapeBackslashes to use preferred style
* No backslash escaping
* Make requested fixes
2025-01-14 04:28:04 +01:00
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{
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"instance": "_1415_",
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"cell": "sky130_fd_sc_hd__dfrtp_1",
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"verilog_src": "synthesis/tests/counter.v:22.3-28.6",
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"pin": "_1415_/Q",
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"net": "mid",
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"arrival": 3.296e-10,
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"capacitance": 1.949e-15,
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"slew": 3.612e-11
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},
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{
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"instance": "_1416_[0]",
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"cell": "sky130_fd_sc_hd__dfrtp_1",
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"verilog_src": "synthesis/tests/counter.v:22.3-28.6",
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"pin": "_1416_[0]/D",
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"net": "mid",
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"arrival": 3.296e-10,
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"slew": 3.612e-11
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}
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],
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"target_clock": "clk",
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"target_clock_edge": "rise",
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"target_clock_path": [
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{
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"instance": "",
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"cell": "counter",
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"verilog_src": "",
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"pin": "clk",
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"arrival": 0.000e+00,
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"capacitance": 3.742e-15,
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"slew": 0.000e+00
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},
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{
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"instance": "_1416_[0]",
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"cell": "sky130_fd_sc_hd__dfrtp_1",
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"verilog_src": "synthesis/tests/counter.v:22.3-28.6",
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"pin": "_1416_[0]/CLK",
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"net": "clk",
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"arrival": 0.000e+00,
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"slew": 0.000e+00
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}
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],
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"data_arrival_time": 3.296e-10,
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"crpr": 0.000e+00,
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"margin": 1.207e-10,
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"required_time": 9.879e-09,
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"slack": 9.550e-09
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}
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]
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}
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