OpenSTA/test/get_filter.ok

55 lines
1.0 KiB
Plaintext
Raw Normal View History

[get_cells -filter liberty_cell==BUFx2_ASAP7_75t_R *]
2024-08-13 04:40:49 +02:00
u1
[get_clocks -filter is_virtual==0 *]
2024-08-13 04:40:49 +02:00
clk
[get_clocks -filter is_virtual==1 *]
2024-08-13 04:40:49 +02:00
vclk
[get_clocks -filter is_virtual *]
vclk
[get_clocks -filter is_virtual&&is_generated *]
[get_clocks -filter is_virtual&&is_generated==0 *]
vclk
[get_clocks -filter is_virtual||is_generated *]
vclk
[get_clocks -filter is_virtual==0||is_generated *]
clk
[get_lib_cells -filter is_buffer==1 *]
2024-08-13 05:50:21 +02:00
asap7_small/BUFx2_ASAP7_75t_R
[get_lib_cells -filter is_inverter==0 *]
2024-08-13 05:50:21 +02:00
asap7_small/AND2x2_ASAP7_75t_R
asap7_small/BUFx2_ASAP7_75t_R
asap7_small/DFFHQx4_ASAP7_75t_R
[get_lib_pins -filter direction==input BUFx2_ASAP7_75t_R/*]
2024-08-13 04:40:49 +02:00
A
[get_lib_pins -filter direction==output BUFx2_ASAP7_75t_R/*]
2024-08-13 04:40:49 +02:00
Y
[get_libs -filter name==asap7_small *]
2024-08-13 05:50:21 +02:00
asap7_small
[get_nets -filter name=~*q *]
2024-08-13 04:40:49 +02:00
r1q
r2q
[get_pins -filter direction==input *]
2024-08-13 04:40:49 +02:00
r1/CLK
r1/D
r2/CLK
r2/D
r3/CLK
r3/D
u1/A
u2/A
u2/B
[get_pins -filter direction==output *]
2024-08-13 04:40:49 +02:00
r1/Q
r2/Q
r3/Q
u1/Y
u2/Y
[get_ports -filter direction==input *]
2024-08-13 04:40:49 +02:00
clk1
clk2
clk3
in1
in2
[get_ports -filter direction==output *]
2024-08-13 04:40:49 +02:00
out