32 lines
1.4 KiB
Tcl
32 lines
1.4 KiB
Tcl
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# Read in design and libraries
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read_liberty asap7_invbuf.lib.gz
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read_liberty asap7_seq.lib.gz
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read_liberty asap7_simple.lib.gz
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read_verilog reg1_asap7.v
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link_design top
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create_clock -name clk -period 500 {clk1 clk2 clk3}
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create_clock -name vclk -period 1000
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# Test filters for each SDC command
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puts "get_cells"
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puts [report_object_full_names [get_cells -filter liberty_cell==BUFx2_ASAP7_75t_R *]]
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puts "get_clocks"
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puts [report_object_full_names [get_clocks -filter is_virtual==0 *]]
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puts [report_object_full_names [get_clocks -filter is_virtual==1 *]]
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puts "get_lib_cells"
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puts [report_object_full_names [get_lib_cells -filter is_buffer==1 *]]
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puts [report_object_full_names [get_lib_cells -filter is_inverter==1 *]]
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puts "get_lib_pins"
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puts [report_object_full_names [get_lib_pins -filter direction==input BUFx2_ASAP7_75t_R/*]]
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puts [report_object_full_names [get_lib_pins -filter direction==output BUFx2_ASAP7_75t_R/*]]
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puts "get_libs"
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puts [report_object_full_names [get_libs -filter name==asap7sc7p5t_INVBUF_RVT_TT_ccs_211120 *]]
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puts "get_nets"
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puts [report_object_full_names [get_nets -filter name=~*q *]]
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puts "get_pins"
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puts [report_object_full_names [get_pins -filter direction==input *]]
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puts [report_object_full_names [get_pins -filter direction==output *]]
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puts "get_ports"
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puts [report_object_full_names [get_ports -filter direction==input *]]
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puts [report_object_full_names [get_ports -filter direction==output *]]
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