OpenSTA/dcalc/ParallelDelayCalc.cc

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DelayCalc reorg commit 410ed56c2c2d0d7afb0e84d0c65d5ff75234e9e3 Author: James Cherry <cherry@parallaxsw.com> Date: Sun Nov 19 08:44:13 2023 -0700 ArcDelayCalcBase -> DelayCalcBase Signed-off-by: James Cherry <cherry@parallaxsw.com> commit 1fdfebe2838c47f6c1866c8a10b14df6439506e0 Author: James Cherry <cherry@parallaxsw.com> Date: Sun Nov 19 08:25:36 2023 -0700 LumpedCapDelayCalc::inputPortDelay Signed-off-by: James Cherry <cherry@parallaxsw.com> commit 3a5e1d01aaff240b2f71d006d620ccd6a70bce6d Author: James Cherry <cherry@parallaxsw.com> Date: Fri Nov 17 16:32:32 2023 -0700 gateDelayInit cleanup Signed-off-by: James Cherry <cherry@parallaxsw.com> commit d0133319126ae4a488a7b31679fbf6507c7f6266 Author: James Cherry <cherry@parallaxsw.com> Date: Fri Nov 17 15:36:12 2023 -0700 mv RCDelayCalc to ArcDelayCalcBase Signed-off-by: James Cherry <cherry@parallaxsw.com> commit fd028e6ba5e092243a84685eb1756a8e4e4bad76 Author: James Cherry <cherry@parallaxsw.com> Date: Fri Nov 17 14:32:53 2023 -0700 ArcDelayCalcBase Signed-off-by: James Cherry <cherry@parallaxsw.com> commit 0ce9cf4c766f7419b998b40aed5af14df97249f1 Author: James Cherry <cherry@parallaxsw.com> Date: Fri Nov 17 10:57:41 2023 -0700 ParallelArcDelayCalc -> ParallelDelayCalc Signed-off-by: James Cherry <cherry@parallaxsw.com> commit 7fa7db6b252f1450fa5b546f5d33d8cb8a94d4bb Author: James Cherry <cherry@parallaxsw.com> Date: Fri Nov 17 08:45:01 2023 -0700 parallelGateDelay args Signed-off-by: James Cherry <cherry@parallaxsw.com> commit 6b85756774ce049c0f5f123f6d60ebbcd62cdd2b Author: James Cherry <cherry@parallaxsw.com> Date: Thu Nov 16 19:55:20 2023 -0700 TimingModel cell_ Signed-off-by: James Cherry <cherry@parallaxsw.com> commit e536d6b0ca0d01e2ad8bd609ad20f9a02497d8f5 Author: James Cherry <cherry@parallaxsw.com> Date: Thu Nov 16 18:07:11 2023 -0700 TimingModel cell_ Signed-off-by: James Cherry <cherry@parallaxsw.com> commit d2d622da4206e06d176e4ae741334fde8df35007 Author: James Cherry <cherry@parallaxsw.com> Date: Thu Nov 16 17:21:15 2023 -0700 rm drvr_cell from arc dcalc funcs Signed-off-by: James Cherry <cherry@parallaxsw.com> commit 522961e8f58bc1a0f0530a0a5218086280a2bcb0 Author: James Cherry <cherry@parallaxsw.com> Date: Thu Nov 16 16:24:34 2023 -0700 tr -> rf Signed-off-by: James Cherry <cherry@parallaxsw.com> commit 29aa0ed40345611b9e3a898342ecc17f6355396f Author: James Cherry <cherry@parallaxsw.com> Date: Thu Nov 16 13:17:44 2023 -0700 GraphDelayCalc Signed-off-by: James Cherry <cherry@parallaxsw.com> commit 934d9f19c52c62925b23ae9b457f14d25e818f1a Author: James Cherry <cherry@parallaxsw.com> Date: Thu Nov 16 12:52:55 2023 -0700 ParallelArcDelayCalc Signed-off-by: James Cherry <cherry@parallaxsw.com> commit d5687d9482ad0f572b017f0ef806ba8e6ff8b6fa Author: James Cherry <cherry@parallaxsw.com> Date: Thu Nov 16 12:16:05 2023 -0700 ParallelArcDelayCalc pvt Signed-off-by: James Cherry <cherry@parallaxsw.com> commit 0de501e5bf2329364b572d1360c18d5aedf3b841 Author: James Cherry <cherry@parallaxsw.com> Date: Thu Nov 16 10:46:22 2023 -0700 ParallelArcDelayCalc::findMultiDrvrGateDelay Signed-off-by: James Cherry <cherry@parallaxsw.com> commit d7457b9e335ed5fa583798e0512914aab6524fcc Author: James Cherry <cherry@parallaxsw.com> Date: Thu Nov 16 10:19:01 2023 -0700 mv multi_drvr_slew_factor_ to ParallelArcDelayCalc Signed-off-by: James Cherry <cherry@parallaxsw.com> commit afec4daa2ab6dd61a2450f1ac8a8cad1ef015a29 Author: James Cherry <cherry@parallaxsw.com> Date: Thu Nov 16 08:02:40 2023 -0700 MultiDrvrNet::net_caps vector Signed-off-by: James Cherry <cherry@parallaxsw.com> commit b450b3a35616ffc8d85610158a91c5d9483b6958 Author: James Cherry <cherry@parallaxsw.com> Date: Thu Nov 16 07:46:43 2023 -0700 sic Signed-off-by: James Cherry <cherry@parallaxsw.com> commit 65767403b3b2ab4e6f7552625accf9aa4766628a Author: James Cherry <cherry@parallaxsw.com> Date: Tue Nov 14 17:49:22 2023 -0700 Sta::connectedCap simplify Signed-off-by: James Cherry <cherry@parallaxsw.com> commit 85bdb8f3362413e7b05f49447a0383140cbb924f Author: James Cherry <cherry@parallaxsw.com> Date: Tue Nov 14 16:43:38 2023 -0700 ParallelArcDelayCalc Signed-off-by: James Cherry <cherry@parallaxsw.com> commit 4feea3ba2277d53697b644d79832e309ce98058a Author: James Cherry <cherry@parallaxsw.com> Date: Tue Nov 14 15:10:18 2023 -0700 mv parallel dcalc to arc delay calc Signed-off-by: James Cherry <cherry@parallaxsw.com> commit 915ed28a2c05acce6569c7933366ef94da8bfaeb Author: James Cherry <cherry@parallaxsw.com> Date: Mon Nov 13 17:47:14 2023 -0700 rm MultiDrvrNet::delays_valid_ Signed-off-by: James Cherry <cherry@parallaxsw.com> commit 2384eb4e5bdca1410c4bf5e23f35bfb49f013e74 Author: James Cherry <cherry@parallaxsw.com> Date: Mon Nov 13 16:02:57 2023 -0700 mkae MultiDrvrNets on the fly Signed-off-by: James Cherry <cherry@parallaxsw.com> Signed-off-by: James Cherry <cherry@parallaxsw.com>
2023-11-19 18:04:45 +01:00
// OpenSTA, Static Timing Analyzer
// Copyright (c) 2023, Parallax Software, Inc.
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <https://www.gnu.org/licenses/>.
#include "ParallelDelayCalc.hh"
#include "TimingArc.hh"
#include "Corner.hh"
#include "Network.hh"
#include "Graph.hh"
#include "Sdc.hh"
#include "Liberty.hh"
#include "GraphDelayCalc.hh"
namespace sta {
ParallelDelayCalc::ParallelDelayCalc(StaState *sta):
DelayCalcBase(sta)
{
}
void
ParallelDelayCalc::inputPortDelay(const Pin *drvr_pin,
float in_slew,
const RiseFall *rf,
const Parasitic *parasitic,
const DcalcAnalysisPt *dcalc_ap)
{
DelayCalcBase::inputPortDelay(drvr_pin, in_slew, rf, parasitic, dcalc_ap);
multi_drvr_slew_factor_ = 1.0;
}
void
ParallelDelayCalc::gateDelayInit(const TimingArc *arc,
const Slew &in_slew,
const Parasitic *drvr_parasitic)
{
DelayCalcBase::gateDelayInit(arc, in_slew, drvr_parasitic);
multi_drvr_slew_factor_ = 1.0F;
}
void
ParallelDelayCalc::findParallelGateDelays(const MultiDrvrNet *multi_drvr,
GraphDelayCalc *dcalc)
{
int count = RiseFall::index_count * corners_->dcalcAnalysisPtCount();
parallel_delays_.resize(count);
parallel_slews_.resize(count);
for (auto dcalc_ap : corners_->dcalcAnalysisPts()) {
for (auto drvr_rf : RiseFall::range()) {
DcalcAPIndex ap_index = dcalc_ap->index();
int drvr_rf_index = drvr_rf->index();
int index = ap_index * RiseFall::index_count + drvr_rf_index;
findMultiDrvrGateDelay(multi_drvr, drvr_rf, dcalc_ap, dcalc,
parallel_delays_[index],
parallel_slews_[index]);
}
}
}
void
ParallelDelayCalc::findMultiDrvrGateDelay(const MultiDrvrNet *multi_drvr,
const RiseFall *drvr_rf,
const DcalcAnalysisPt *dcalc_ap,
GraphDelayCalc *dcalc,
// Return values.
ArcDelay &parallel_delay,
Slew &parallel_slew)
{
ArcDelay delay_sum = 0.0;
Slew slew_sum = 0.0;
for (Vertex *drvr_vertex : *multi_drvr->drvrs()) {
Pin *drvr_pin = drvr_vertex->pin();
Instance *drvr_inst = network_->instance(drvr_pin);
const Pvt *pvt = sdc_->pvt(drvr_inst, dcalc_ap->constraintMinMax());
if (pvt == nullptr)
pvt = dcalc_ap->operatingConditions();
VertexInEdgeIterator edge_iter(drvr_vertex, graph_);
while (edge_iter.hasNext()) {
Edge *edge = edge_iter.next();
TimingArcSet *arc_set = edge->timingArcSet();
const LibertyPort *related_out_port = arc_set->relatedOut();
for (TimingArc *arc : arc_set->arcs()) {
RiseFall *arc_rf = arc->toEdge()->asRiseFall();
if (arc_rf == drvr_rf) {
Vertex *from_vertex = edge->from(graph_);
RiseFall *from_rf = arc->fromEdge()->asRiseFall();
Slew from_slew = dcalc->edgeFromSlew(from_vertex, from_rf,
edge, dcalc_ap);
ArcDelay intrinsic_delay;
Slew intrinsic_slew;
gateDelay(arc, from_slew, 0.0, 0, 0.0, pvt, dcalc_ap,
intrinsic_delay, intrinsic_slew);
Parasitic *parasitic = findParasitic(drvr_pin, drvr_rf, dcalc_ap);
const Pin *related_out_pin = 0;
float related_out_cap = 0.0;
if (related_out_port) {
Instance *inst = network_->instance(drvr_pin);
related_out_pin = network_->findPin(inst, related_out_port);
if (related_out_pin) {
Parasitic *related_out_parasitic = findParasitic(related_out_pin,
drvr_rf,
dcalc_ap);
related_out_cap = dcalc->loadCap(related_out_pin,
related_out_parasitic,
drvr_rf, dcalc_ap);
}
}
float load_cap = dcalc->loadCap(drvr_pin, parasitic,
drvr_rf, dcalc_ap);
ArcDelay gate_delay;
Slew gate_slew;
gateDelay(arc, from_slew, load_cap, parasitic,
related_out_cap, pvt, dcalc_ap,
gate_delay, gate_slew);
delay_sum += 1.0F / (gate_delay - intrinsic_delay);
slew_sum += 1.0F / gate_slew;
}
}
}
}
parallel_delay = 1.0F / delay_sum;
parallel_slew = 1.0F / slew_sum;
}
void
ParallelDelayCalc::parallelGateDelay(const Pin *,
const TimingArc *arc,
const Slew &from_slew,
float load_cap,
const Parasitic *drvr_parasitic,
float related_out_cap,
const Pvt *pvt,
const DcalcAnalysisPt *dcalc_ap,
// Return values.
ArcDelay &gate_delay,
Slew &gate_slew)
{
ArcDelay intrinsic_delay;
Slew intrinsic_slew;
gateDelay(arc, from_slew, 0.0, 0, 0.0, pvt, dcalc_ap,
intrinsic_delay, intrinsic_slew);
const RiseFall *drvr_rf = arc->toEdge()->asRiseFall();
int index = dcalc_ap->index() * RiseFall::index_count + drvr_rf->index();
ArcDelay parallel_delay = parallel_delays_[index];
Slew parallel_slew = parallel_slews_[index];
gate_delay = parallel_delay + intrinsic_delay;
gate_slew = parallel_slew;
Delay gate_delay1;
Slew gate_slew1;
gateDelay(arc, from_slew, load_cap, drvr_parasitic,
related_out_cap, pvt, dcalc_ap,
gate_delay1, gate_slew1);
float factor = delayRatio(gate_slew, gate_slew1);
multi_drvr_slew_factor_ = factor;
}
} // namespace