9 lines
251 B
Coq
9 lines
251 B
Coq
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// Verilog with assign statement
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// This triggers VerilogStmt::isAssign, VerilogAssign
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module assign_mod (input in1, input in2, output out1);
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wire a, b;
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assign a = in1;
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assign b = in2;
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AND2x2_ASAP7_75t_R u1 (.A(a), .B(b), .Y(out1));
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endmodule
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