OpenSTA/verilog/VerilogWriter.hh

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2019-06-17 06:08:00 +02:00
// OpenSTA, Static Timing Analyzer
// Copyright (c) 2019, Parallax Software, Inc.
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <https://www.gnu.org/licenses/>.
#ifndef STA_WRITE_VERILOG_H
#define STA_WRITE_VERILOG_H
namespace sta {
class Network;
void
writeVerilog(const char *filename,
bool sorted,
Network *network);
} // namespace
#endif