2018-09-28 17:54:21 +02:00
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// OpenSTA, Static Timing Analyzer
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2019-01-01 21:26:11 +01:00
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// Copyright (c) 2019, Parallax Software, Inc.
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2018-09-28 17:54:21 +02:00
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <https://www.gnu.org/licenses/>.
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#ifndef STA_READ_VERILOG_H
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#define STA_READ_VERILOG_H
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namespace sta {
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class Report;
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class Debug;
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class Cell;
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class NetworkEdit;
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class Instance;
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// Return true if successful.
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bool
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readVerilogFile(const char *filename, Report *report, Debug *debug,
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NetworkReader *network);
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void
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deleteVerilogReader();
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} // namespace
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#endif
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