test: strengthen assertions, add sorted SDC diff, and clean up tests
- Split oversized test files to stay under 5,000 lines per file:
TestSdc.cc → TestSdcClasses.cc, TestSdcStaInit.cc, TestSdcStaDesign.cc
TestSearchStaDesign.cc → TestSearchStaDesign.cc, TestSearchStaDesignB.cc
TestLibertyStaBasics.cc → TestLibertyStaBasics.cc, TestLibertyStaBasicsB.cc
TestNetwork.cc → TestNetwork.cc, TestNetworkB.cc
- Replace ~200+ (void) casts with proper EXPECT_* assertions across all
C++ test files (dcalc, liberty, network, sdc, search, power, spice, util)
- Remove ~55 SUCCEED() and EXPECT_TRUE(true) no-op assertions
- Fix 6 load-only Tcl tests by adding diff_files verification with
22 new .sdcok golden reference files
- Delete 7 orphan .ok files with no matching .tcl tests
- Add how_to_write_good_tests.md and TODO6.md documenting test quality rules
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>
2026-02-23 09:36:45 +01:00
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INV equiv count: 6
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BUF equiv count: 9
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NAND2 equiv count: 3
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NAND3 equiv count: 3
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NAND4 equiv count: 3
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NOR2 equiv count: 3
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NOR3 equiv count: 3
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NOR4 equiv count: 3
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AND2 equiv count: 3
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OR2 equiv count: 3
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AOI21 equiv count: 3
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OAI21 equiv count: 3
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DFF equiv count: 2
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SDFF equiv count: 2
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CLKBUF equiv count: 9
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XOR2 equiv count: 2
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INV_X1 typ equiv fast: 1
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INV_X1 typ equiv slow: 1
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INV_X1 fast equiv slow: 1
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BUF_X1 typ equiv fast: 1
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NAND2_X1 typ equiv fast: 1
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DFF_X1 typ equiv fast: 1
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equiv_cell_ports INV typ/fast: 1
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equiv_cell_ports BUF typ/fast: 1
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equiv_cell_ports INV/BUF: 0
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equiv_cell_ports NAND2/NAND3: 0
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equiv_cell_timing_arcs INV typ/fast: 1
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equiv_cell_timing_arcs BUF typ/fast: 1
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equiv_cell_timing_arcs INV/BUF: 0
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typ library buffers: 9
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fast library buffers: 9
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slow library buffers: 9
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INV_X1 equiv INV_X2: 1
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INV_X1 equiv INV_X4: 1
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INV_X1 equiv INV_X8: 1
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INV_X1 equiv INV_X16: 1
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INV_X1 equiv INV_X32: 1
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NAND2 equiv NOR2: 0
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AND2 equiv OR2: 0
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AOI21 equiv OAI21: 0
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DFF equiv DFFR: 0
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DFF equiv DFFS: 0
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DFFR equiv DFFRS: 0
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LVT INV equiv count: 6
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LVT library buffers: 9
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INV_X1 equiv LVT INV_X1_L: 1
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equiv_cell_ports INV/LVT_INV: 1
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