21 lines
1.0 KiB
Tcl
21 lines
1.0 KiB
Tcl
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# write_path_spice ties non-unate side inputs to the sensitized arc (issue #474)
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source helpers.tcl
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read_liberty write_path_spice_arc_sense.lib.gz
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read_verilog write_path_spice_arc_sense.v
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link_design repro
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create_clock -name vclk -period 10
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set_input_delay -clock vclk 0 [all_inputs]
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set_output_delay -clock vclk 0 [all_outputs]
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# Force the inverting arc B(fall) -> X(rise), which the liberty defines only
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# under "when A" (A=1). The xor2 side input A is the unconstrained port s, so
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# a correct deck must tie x0/A high (v1 x0/A 0 1.800). Before the fix the
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# Boolean-difference cube ignored the arc direction and tied it low (0.000).
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set spice_file [make_result_file "write_path_spice_arc_sense.sp"]
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write_path_spice -path_args {-path_delay max -fall_from [get_ports a] -rise_to [get_ports x]} \
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-spice_file $spice_file \
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-lib_subckt_file write_path_spice_arc_sense.cells.spice \
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-model_file write_path_spice_arc_sense.models.spice \
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-power VPWR -ground VGND \
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-simulator ngspice
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report_file ${spice_file}_1.sp
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