OpenSTA/test/write_path_spice_arc_sense.ok

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write_path_spice: match side input values to the path arc's transitions (#475) * write_path_spice: match side input values to the path arc's transitions gatePortValues() chose side input values from the first CUDD cube of the Boolean difference d(f)/d(input), which sensitizes the gate but ignores the transition directions of the arc the path used: - For non-unate gates whose Boolean difference is a tautology (xor2, xnor2) every side variable came back don't-care, and the unknown value fell through to tie-low in writeSubcktInstVoltSrcs() -- wrong whenever the path used the when-condition requiring the side high. - For mux select arcs the cube was an arbitrary data assignment, unrelated to the output edge the path reported. Either way the written deck's gate drives the opposite direction from the reported path: the simulated chain switches with inverted polarity from that gate onward, edge-qualified arrival measurements fail, and the deck sums delays from the wrong rise/fall tables. Constrain the side input condition to the cofactor pair matching this arc -- f1 & !f0 when the input and driver edges agree (non-inverting), f0 & !f1 when they differ (inverting) -- threading the gate input RiseFall from the path stage into gatePortValues(). Also release the CUDD nodes that were previously leaked (the old code Cudd_Ref'd the Boolean difference after the generator was freed and never deref'd it). Fixes #474 Co-Authored-By: Claude Fable 5 <noreply@anthropic.com> * test: write_path_spice arc-sense regression for #474, and outlined in #475 --------- Co-authored-by: Brian Degnan <bpdegnan@users.noreply.github.com> Co-authored-by: Claude Fable 5 <noreply@anthropic.com>
2026-07-27 19:23:15 +02:00
Warning 1171: write_path_spice_arc_sense.lib.gz line 23, default_fanout_load is 0.0.
* Path from a v to x ^
.include "write_path_spice_arc_sense.models.spice"
.include "write_path_spice_arc_sense.sp_1.subckt"
.tran 1e-13 3.33e-09
.print tran v(a) v(x0/B) v(x0/X) v(x)
**************
* Input source
**************
v1 a 0 pwl(
+0.000e+00 1.800e+00
+1.667e-11 0.000e+00
+3.333e-09 0.000e+00
+)
*****************
* Stage instances
*****************
xstage1 a x0/B stage1
xstage2 x0/B x0/X x stage2
***************
* Stage subckts
***************
.subckt stage1 a x0/B
* Net a
* Net has no parasitics.
R1 a x0/B 1.000e-04
.ends
.subckt stage2 x0/B x0/X x
* Gate x0 B -> X
xx0 x0/A x0/B x0/VGND x0/VNB x0/VPB x0/VPWR x0/X sky130_fd_sc_hd__xor2_1
v1 x0/A 0 1.800
v2 x0/VGND 0 0.000
v3 x0/VNB 0 0.000
v4 x0/VPB 0 1.800
v5 x0/VPWR 0 1.800
* Load pins
* Net x
* Net has no parasitics.
R1 x0/X x 1.000e-04
.ends
.end