Add {`instance`, `cell`, `verilog_src`, `pin`, `net`, `hier_pins`, `capacitance`} fields to `report_checks -format json` for paths (#135)
* Add {`inst`, `cell`, `src`, `nets`} to `report_checks -format json`
* Smallfix
* Improved nets
* Race condition fix
* Fixes
* Small whitespace fix
* Add no paths corner case stuff
* Adjustments to naming of fields
* Requested fixes
* Reintroduce escapeBackslashes, use stringCopy to prevent stack memory warning
* Fix escapeBackslashes to use preferred style
* No backslash escaping
* Make requested fixes
2025-01-14 04:28:04 +01:00
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# report_checks -format json
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read_liberty ../examples/sky130hd_tt.lib.gz
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read_verilog verilog_attribute.v
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link_design counter
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create_clock -name clk -period 10 clk
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set_input_delay -clock clk 0 [all_inputs -no_clocks]
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2025-01-15 17:24:53 +01:00
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report_checks -path_group clk -format json
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