30 lines
923 B
Tcl
30 lines
923 B
Tcl
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# disconnect/disconnect pin set_multicycle_path
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read_liberty asap7_small.lib.gz
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read_verilog disconnect_mcp_pin.v
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link_design top
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create_clock -name clk -period 500 clk
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set_input_delay -clock clk 10 data_in[*]
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# This SDC defines setup and hold time requirements for data pins
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# relative to a clock, typical for a source-synchronous interface.
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set_data_check -from clk -to [get_pins u0/A] -setup 10
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set_data_check -from clk -to [get_pins u0/A] -hold 10
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set_data_check -from clk -to [get_pins u1/A] -setup 10
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set_data_check -from clk -to [get_pins u1/A] -hold 10
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set_multicycle_path -end -setup 1 -to [get_pins u0/A]
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set_multicycle_path -end -setup 1 -to [get_pins u1/A]
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set_multicycle_path -start -hold 0 -to [get_pins u0/A]
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set_multicycle_path -start -hold 0 -to [get_pins u1/A]
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report_checks -to u1/A
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disconnect_pin data_in[1] u1/A
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report_checks -to u1/A
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connect_pin data_in[1] u1/A
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report_checks -to u1/A
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