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luke
/
OpenRAM
mirror of
https://github.com/VLSIDA/OpenRAM.git
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fd806077d2
OpenRAM
/
compiler
/
verify
History
Hunter Nichols
fd806077d2
Added class and test for testing the delay of several bitcells.
2018-10-08 15:50:52 -07:00
..
__init__.py
Added class and test for testing the delay of several bitcells.
2018-10-08 15:50:52 -07:00
assura.py
Add DRC/LVS/PEX statistics in verbose=1 mode
2018-07-11 11:59:24 -07:00
calibre.py
Add temporary options to LVS to allow name merging
2018-07-18 15:10:29 -07:00
magic.py
Hard code flatten commands for the unique id precharge array
2018-09-13 15:15:41 -07:00
none.py
Add none option for verify wrapper with warning messages.
2018-09-11 10:17:24 -07:00