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bank.py
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Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport
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2018-09-18 18:56:15 -07:00 |
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bank_select.py
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s_en will be shared amongst the sense amps of different ports, so I'm removing the distinct s_en signals from several modules.
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2018-09-13 18:46:43 -07:00 |
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bitcell.py
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Merging latest changes from multiport with changes made to pbitcell. Changing select code from other modules and tests to reflect changes made to pbitcell.
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2018-09-06 19:36:50 -07:00 |
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bitcell_array.py
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Clean up new code for add_modules, add_pins and netlist/layouts.
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2018-08-28 10:24:09 -07:00 |
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control_logic.py
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Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport
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2018-09-18 18:56:15 -07:00 |
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delay_chain.py
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Make bitcell width/height not static. Update modules to use it for pbitcell.
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2018-09-04 11:55:22 -07:00 |
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dff.py
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Remove ms_flop and replace with dff. Might break setup_hold tests.
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2018-09-13 11:02:28 -07:00 |
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dff_array.py
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Clean up new code for add_modules, add_pins and netlist/layouts.
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2018-08-28 10:24:09 -07:00 |
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dff_buf.py
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Clean up new code for add_modules, add_pins and netlist/layouts.
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2018-08-28 10:24:09 -07:00 |
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dff_buf_array.py
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Clean up new code for add_modules, add_pins and netlist/layouts.
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2018-08-28 10:24:09 -07:00 |
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dff_inv.py
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Clean up new code for add_modules, add_pins and netlist/layouts.
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2018-08-28 10:24:09 -07:00 |
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dff_inv_array.py
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Found rotate bug in transformCoordinate. Cleaned up transFlags.
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2018-09-04 16:35:40 -07:00 |
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hierarchical_decoder.py
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Make bitcell width/height not static. Update modules to use it for pbitcell.
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2018-09-04 11:55:22 -07:00 |
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hierarchical_predecode.py
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Add extra track spacings in some routes.
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2018-09-13 14:12:24 -07:00 |
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hierarchical_predecode2x4.py
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Converted all modules to not run create_layout when netlist_only
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2018-08-27 16:42:48 -07:00 |
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hierarchical_predecode3x8.py
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Converted all modules to not run create_layout when netlist_only
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2018-08-27 16:42:48 -07:00 |
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multibank.py
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Updating ms_flop removal.
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2018-09-13 11:40:24 -07:00 |
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precharge_array.py
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Clean up new code for add_modules, add_pins and netlist/layouts.
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2018-08-28 10:24:09 -07:00 |
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replica_bitcell.py
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Finish renaming replica bitcell and bitline pin names.
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2018-09-04 14:03:15 -07:00 |
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replica_bitline.py
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Adding replica_pbitcell and test for multi-ported purposes. Altering replica bitline and test to accomodate.
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2018-09-13 01:42:06 -07:00 |
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replica_pbitcell.py
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Correcting format of replica_pbitcell.
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2018-09-13 18:51:52 -07:00 |
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sense_amp.py
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Fixed comment style on power functions. Also added power parameters to scn3me_subm tech file and tested functionality.
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2018-03-01 23:34:15 -08:00 |
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sense_amp_array.py
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Make bitcell width/height not static. Update modules to use it for pbitcell.
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2018-09-04 11:55:22 -07:00 |
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single_level_column_mux_array.py
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Bank level layout now works with pbitcell and 1RW. Column mux and array have been altered to accomodate multiport. Multiport changes to wordline driver were removed because they were unnecessary.
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2018-09-09 22:06:29 -07:00 |
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tri_gate.py
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Fixed comment style on power functions. Also added power parameters to scn3me_subm tech file and tested functionality.
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2018-03-01 23:34:15 -08:00 |
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tri_gate_array.py
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Clean up new code for add_modules, add_pins and netlist/layouts.
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2018-08-28 10:24:09 -07:00 |
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wordline_driver.py
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Bank level layout now works with pbitcell and 1RW. Column mux and array have been altered to accomodate multiport. Multiport changes to wordline driver were removed because they were unnecessary.
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2018-09-09 22:06:29 -07:00 |
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write_driver.py
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Organize top-level files into subdirs.
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2018-02-09 10:25:24 -08:00 |
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write_driver_array.py
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Make bitcell width/height not static. Update modules to use it for pbitcell.
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2018-09-04 11:55:22 -07:00 |
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