Michael Timothy Grimes fc5f163828 Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport

2018-09-18 18:56:15 -07:00

..

bank_select.py

s_en will be shared amongst the sense amps of different ports, so I'm removing the distinct s_en signals from several modules.

2018-09-13 18:46:43 -07:00

bank.py

Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport

2018-09-18 18:56:15 -07:00

bitcell_array.py

Clean up new code for add_modules, add_pins and netlist/layouts.

2018-08-28 10:24:09 -07:00

bitcell.py

Merging latest changes from multiport with changes made to pbitcell. Changing select code from other modules and tests to reflect changes made to pbitcell.

2018-09-06 19:36:50 -07:00

control_logic.py

Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport

2018-09-18 18:56:15 -07:00

delay_chain.py

Make bitcell width/height not static. Update modules to use it for pbitcell.

2018-09-04 11:55:22 -07:00

dff_array.py

Clean up new code for add_modules, add_pins and netlist/layouts.

2018-08-28 10:24:09 -07:00

dff_buf_array.py

Clean up new code for add_modules, add_pins and netlist/layouts.

2018-08-28 10:24:09 -07:00

dff_buf.py

Clean up new code for add_modules, add_pins and netlist/layouts.

2018-08-28 10:24:09 -07:00

dff_inv_array.py

Found rotate bug in transformCoordinate. Cleaned up transFlags.

2018-09-04 16:35:40 -07:00

dff_inv.py

Clean up new code for add_modules, add_pins and netlist/layouts.

2018-08-28 10:24:09 -07:00

dff.py

Remove ms_flop and replace with dff. Might break setup_hold tests.

2018-09-13 11:02:28 -07:00

hierarchical_decoder.py

Make bitcell width/height not static. Update modules to use it for pbitcell.

2018-09-04 11:55:22 -07:00

hierarchical_predecode2x4.py

Converted all modules to not run create_layout when netlist_only

2018-08-27 16:42:48 -07:00

hierarchical_predecode3x8.py

Converted all modules to not run create_layout when netlist_only

2018-08-27 16:42:48 -07:00

hierarchical_predecode.py

Add extra track spacings in some routes.

2018-09-13 14:12:24 -07:00

multibank.py

Updating ms_flop removal.

2018-09-13 11:40:24 -07:00

precharge_array.py

Clean up new code for add_modules, add_pins and netlist/layouts.

2018-08-28 10:24:09 -07:00

replica_bitcell.py

Finish renaming replica bitcell and bitline pin names.

2018-09-04 14:03:15 -07:00

replica_bitline.py

Adding replica_pbitcell and test for multi-ported purposes. Altering replica bitline and test to accomodate.

2018-09-13 01:42:06 -07:00

replica_pbitcell.py

Correcting format of replica_pbitcell.

2018-09-13 18:51:52 -07:00

sense_amp_array.py

Make bitcell width/height not static. Update modules to use it for pbitcell.

2018-09-04 11:55:22 -07:00

sense_amp.py

Fixed comment style on power functions. Also added power parameters to scn3me_subm tech file and tested functionality.

2018-03-01 23:34:15 -08:00

single_level_column_mux_array.py

Bank level layout now works with pbitcell and 1RW. Column mux and array have been altered to accomodate multiport. Multiport changes to wordline driver were removed because they were unnecessary.

2018-09-09 22:06:29 -07:00

tri_gate_array.py

Clean up new code for add_modules, add_pins and netlist/layouts.

2018-08-28 10:24:09 -07:00

tri_gate.py

Fixed comment style on power functions. Also added power parameters to scn3me_subm tech file and tested functionality.

2018-03-01 23:34:15 -08:00

wordline_driver.py

Bank level layout now works with pbitcell and 1RW. Column mux and array have been altered to accomodate multiport. Multiport changes to wordline driver were removed because they were unnecessary.

2018-09-09 22:06:29 -07:00

write_driver_array.py

Make bitcell width/height not static. Update modules to use it for pbitcell.

2018-09-04 11:55:22 -07:00

write_driver.py

Organize top-level files into subdirs.

2018-02-09 10:25:24 -08:00