mirror of https://github.com/VLSIDA/OpenRAM.git
343 lines
9.5 KiB
Plaintext
343 lines
9.5 KiB
Plaintext
library (sram_8_128_scn4m_subm_FF_5p0V_25C_lib){
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delay_model : "table_lookup";
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time_unit : "1ns" ;
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voltage_unit : "1V" ;
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current_unit : "1mA" ;
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resistance_unit : "1kohm" ;
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capacitive_load_unit(1, pF) ;
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leakage_power_unit : "1mW" ;
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pulling_resistance_unit :"1kohm" ;
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operating_conditions(OC){
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process : 1.0 ;
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voltage : 5.0 ;
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temperature : 25;
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}
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input_threshold_pct_fall : 50.0 ;
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output_threshold_pct_fall : 50.0 ;
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input_threshold_pct_rise : 50.0 ;
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output_threshold_pct_rise : 50.0 ;
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slew_lower_threshold_pct_fall : 10.0 ;
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slew_upper_threshold_pct_fall : 90.0 ;
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slew_lower_threshold_pct_rise : 10.0 ;
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slew_upper_threshold_pct_rise : 90.0 ;
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nom_voltage : 5.0;
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nom_temperature : 25;
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nom_process : 1.0;
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default_cell_leakage_power : 0.0 ;
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default_leakage_power_density : 0.0 ;
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default_input_pin_cap : 1.0 ;
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default_inout_pin_cap : 1.0 ;
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default_output_pin_cap : 0.0 ;
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default_max_transition : 0.5 ;
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default_fanout_load : 1.0 ;
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default_max_fanout : 4.0 ;
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default_connection_class : universal ;
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voltage_map ( VDD, 5.0 );
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voltage_map ( GND, 0 );
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lu_table_template(CELL_TABLE){
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variable_1 : input_net_transition;
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variable_2 : total_output_net_capacitance;
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index_1("0.0125, 0.05, 0.4");
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index_2("0.00245605, 0.0098242, 0.0392968");
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}
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lu_table_template(CONSTRAINT_TABLE){
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variable_1 : related_pin_transition;
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variable_2 : constrained_pin_transition;
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index_1("0.0125, 0.05, 0.4");
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index_2("0.0125, 0.05, 0.4");
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}
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default_operating_conditions : OC;
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type (data){
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base_type : array;
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data_type : bit;
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bit_width : 8;
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bit_from : 0;
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bit_to : 7;
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}
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type (addr){
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base_type : array;
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data_type : bit;
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bit_width : 7;
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bit_from : 0;
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bit_to : 6;
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}
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cell (sram_8_128_scn4m_subm){
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memory(){
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type : ram;
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address_width : 7;
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word_width : 8;
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}
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interface_timing : true;
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dont_use : true;
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map_only : true;
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dont_touch : true;
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area : 0;
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pg_pin(vdd) {
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voltage_name : VDD;
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pg_type : primary_power;
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}
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pg_pin(gnd) {
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voltage_name : GND;
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pg_type : primary_ground;
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}
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leakage_power () {
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value : 0.001282;
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}
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cell_leakage_power : 0.001282;
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bus(din0){
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bus_type : data;
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direction : input;
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capacitance : 0.0098242;
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memory_write(){
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address : addr0;
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clocked_on : clk0;
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}
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pin(din0[7:0]){
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timing(){
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timing_type : setup_rising;
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related_pin : "clk0";
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rise_constraint(CONSTRAINT_TABLE) {
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values("0.009, 0.009, 0.009",\
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"0.009, 0.009, 0.009",\
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"0.009, 0.009, 0.009");
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}
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fall_constraint(CONSTRAINT_TABLE) {
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values("0.009, 0.009, 0.009",\
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"0.009, 0.009, 0.009",\
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"0.009, 0.009, 0.009");
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}
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}
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timing(){
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timing_type : hold_rising;
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related_pin : "clk0";
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rise_constraint(CONSTRAINT_TABLE) {
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values("0.001, 0.001, 0.001",\
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"0.001, 0.001, 0.001",\
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"0.001, 0.001, 0.001");
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}
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fall_constraint(CONSTRAINT_TABLE) {
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values("0.001, 0.001, 0.001",\
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"0.001, 0.001, 0.001",\
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"0.001, 0.001, 0.001");
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}
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}
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}
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}
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bus(dout0){
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bus_type : data;
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direction : output;
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max_capacitance : 0.0392968;
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min_capacitance : 0.00245605;
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memory_read(){
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address : addr0;
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}
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pin(dout0[7:0]){
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timing(){
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timing_sense : non_unate;
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related_pin : "clk0";
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timing_type : falling_edge;
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cell_rise(CELL_TABLE) {
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values("1.938, 1.954, 2.019",\
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"1.938, 1.954, 2.019",\
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"1.938, 1.954, 2.019");
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}
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cell_fall(CELL_TABLE) {
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values("1.938, 1.954, 2.019",\
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"1.938, 1.954, 2.019",\
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"1.938, 1.954, 2.019");
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}
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rise_transition(CELL_TABLE) {
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values("0.006, 0.007, 0.014",\
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"0.006, 0.007, 0.014",\
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"0.006, 0.007, 0.014");
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}
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fall_transition(CELL_TABLE) {
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values("0.006, 0.007, 0.014",\
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"0.006, 0.007, 0.014",\
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"0.006, 0.007, 0.014");
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}
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}
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}
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}
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bus(addr0){
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bus_type : addr;
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direction : input;
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capacitance : 0.0098242;
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max_transition : 0.4;
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pin(addr0[6:0]){
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timing(){
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timing_type : setup_rising;
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related_pin : "clk0";
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rise_constraint(CONSTRAINT_TABLE) {
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values("0.009, 0.009, 0.009",\
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"0.009, 0.009, 0.009",\
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"0.009, 0.009, 0.009");
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}
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fall_constraint(CONSTRAINT_TABLE) {
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values("0.009, 0.009, 0.009",\
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"0.009, 0.009, 0.009",\
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"0.009, 0.009, 0.009");
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}
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}
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timing(){
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timing_type : hold_rising;
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related_pin : "clk0";
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rise_constraint(CONSTRAINT_TABLE) {
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values("0.001, 0.001, 0.001",\
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"0.001, 0.001, 0.001",\
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"0.001, 0.001, 0.001");
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}
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fall_constraint(CONSTRAINT_TABLE) {
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values("0.001, 0.001, 0.001",\
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"0.001, 0.001, 0.001",\
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"0.001, 0.001, 0.001");
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}
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}
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}
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}
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pin(csb0){
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direction : input;
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capacitance : 0.0098242;
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timing(){
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timing_type : setup_rising;
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related_pin : "clk0";
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rise_constraint(CONSTRAINT_TABLE) {
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values("0.009, 0.009, 0.009",\
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"0.009, 0.009, 0.009",\
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"0.009, 0.009, 0.009");
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}
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fall_constraint(CONSTRAINT_TABLE) {
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values("0.009, 0.009, 0.009",\
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"0.009, 0.009, 0.009",\
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"0.009, 0.009, 0.009");
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}
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}
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timing(){
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timing_type : hold_rising;
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related_pin : "clk0";
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rise_constraint(CONSTRAINT_TABLE) {
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values("0.001, 0.001, 0.001",\
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"0.001, 0.001, 0.001",\
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"0.001, 0.001, 0.001");
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}
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fall_constraint(CONSTRAINT_TABLE) {
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values("0.001, 0.001, 0.001",\
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"0.001, 0.001, 0.001",\
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"0.001, 0.001, 0.001");
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}
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}
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}
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pin(web0){
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direction : input;
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capacitance : 0.0098242;
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timing(){
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timing_type : setup_rising;
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related_pin : "clk0";
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rise_constraint(CONSTRAINT_TABLE) {
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values("0.009, 0.009, 0.009",\
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"0.009, 0.009, 0.009",\
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"0.009, 0.009, 0.009");
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}
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fall_constraint(CONSTRAINT_TABLE) {
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values("0.009, 0.009, 0.009",\
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"0.009, 0.009, 0.009",\
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"0.009, 0.009, 0.009");
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}
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}
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timing(){
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timing_type : hold_rising;
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related_pin : "clk0";
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rise_constraint(CONSTRAINT_TABLE) {
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values("0.001, 0.001, 0.001",\
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"0.001, 0.001, 0.001",\
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"0.001, 0.001, 0.001");
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}
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fall_constraint(CONSTRAINT_TABLE) {
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values("0.001, 0.001, 0.001",\
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"0.001, 0.001, 0.001",\
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"0.001, 0.001, 0.001");
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}
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}
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}
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pin(clk0){
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clock : true;
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direction : input;
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capacitance : 0.0098242;
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internal_power(){
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when : "!csb0 & !web0";
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rise_power(scalar){
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values("1.375767e+01");
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}
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fall_power(scalar){
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values("1.375767e+01");
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}
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}
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internal_power(){
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when : "csb0 & !web0";
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rise_power(scalar){
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values("1.375767e+01");
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}
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fall_power(scalar){
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values("1.375767e+01");
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}
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}
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internal_power(){
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when : "!csb0 & web0";
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rise_power(scalar){
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values("1.375767e+01");
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}
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fall_power(scalar){
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values("1.375767e+01");
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}
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}
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internal_power(){
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when : "csb0 & web0";
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rise_power(scalar){
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values("1.375767e+01");
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}
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fall_power(scalar){
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values("1.375767e+01");
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}
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}
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timing(){
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timing_type :"min_pulse_width";
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related_pin : clk0;
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rise_constraint(scalar) {
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values("0.202");
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}
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fall_constraint(scalar) {
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values("0.202");
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}
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}
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timing(){
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timing_type :"minimum_period";
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related_pin : clk0;
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rise_constraint(scalar) {
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values("0.404");
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}
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fall_constraint(scalar) {
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values("0.404");
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}
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}
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}
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}
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}
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