mirror of https://github.com/VLSIDA/OpenRAM.git
19 lines
437 B
SourcePawn
19 lines
437 B
SourcePawn
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*********************** "cell_6t" ******************************
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.SUBCKT replica_cell_6t bl br wl vdd gnd
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* SPICE3 file created from cell_6t.ext - technology: scmos
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* Inverter 1
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M1000 Q vdd vdd vdd p w=0.6u l=0.8u
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M1002 Q vdd gnd gnd n w=1.6u l=0.4u
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* Inverter 2
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M1001 vdd Q vdd vdd p w=0.6u l=0.8u
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M1003 gnd Q vdd gnd n w=1.6u l=0.4u
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* Access transistors
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M1004 Q wl bl gnd n w=0.8u l=0.4u
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M1005 vdd wl br gnd n w=0.8u l=0.4u
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.ENDS
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