mirror of https://github.com/VLSIDA/OpenRAM.git
15 lines
282 B
Python
15 lines
282 B
Python
word_size = 32
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num_words = 128
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tech_name = "scn4m_subm"
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process_corners = ["TT"]
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supply_voltages = [ 5.0 ]
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temperatures = [ 25 ]
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output_path = "temp"
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output_name = "sram_{0}_{1}_{2}".format(word_size,num_words,tech_name)
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drc_name = "magic"
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lvs_name = "netgen"
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pex_name = "magic"
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