mirror of https://github.com/VLSIDA/OpenRAM.git
53 lines
1.5 KiB
Python
Executable File
53 lines
1.5 KiB
Python
Executable File
#!/usr/bin/env python2.7
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"""
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Run a regresion test on a basic array
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"""
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import unittest
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from testutils import header,openram_test
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import sys,os
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sys.path.append(os.path.join(sys.path[0],".."))
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import globals
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from globals import OPTS
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import debug
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#@unittest.skip("SKIPPING 05_array_multiport_test")
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class array_multiport_test(openram_test):
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def runTest(self):
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globals.init_openram("config_20_{0}".format(OPTS.tech_name))
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global verify
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import verify
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OPTS.check_lvsdrc = False
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import bitcell_array
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OPTS.bitcell = "pbitcell"
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OPTS.rw_ports = 2
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OPTS.r_ports = 2
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OPTS.w_ports = 2
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debug.info(2, "Testing 4x4 array for multiport bitcell, with read ports at the edge of the bit cell")
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a = bitcell_array.bitcell_array(name="pbitcell_array", cols=4, rows=4)
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self.local_check(a)
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OPTS.rw_ports = 2
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OPTS.r_ports = 0
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OPTS.w_ports = 2
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debug.info(2, "Testing 4x4 array for multiport bitcell, with read/write ports at the edge of the bit cell")
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a = bitcell_array.bitcell_array(name="pbitcell_array", cols=4, rows=4)
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self.local_check(a)
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OPTS.check_lvsdrc = True
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globals.end_openram()
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# instantiate a copy of the class to actually run the test
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if __name__ == "__main__":
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(OPTS, args) = globals.parse_args()
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del sys.argv[1:]
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header(__file__, OPTS.tech_name)
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unittest.main()
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