mirror of https://github.com/VLSIDA/OpenRAM.git
101 lines
5.3 KiB
TeX
101 lines
5.3 KiB
TeX
\section{Unit Tests}
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\label{sec:unittests}
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OpenRAM comes with a unit testing framework based on the Python
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unittest framework. Since OpenRAM is technology independent, these
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unit tests can be run in any technology to verify that the technology
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is properly ported. By default, FreePDK45 is supported.
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The unit tests consist of the following tests that test each module/sub-block of OpenRAM:
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\begin{itemize}
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\item \verb|00_code_format_check__test.py| - Checks the format of the codes. returns error if finds $TAB$ in codes.
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\item \verb|01_library_drc_test.py| - DRC of library cells in technology \verb|gds_lib|
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\item \verb|02_library_lvs_test.py| - LVS of library cells in technology \verb|gds_lib| and \verb|sp_lib| %(names must correspond with different extensions)
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\item \verb|03_contact_test.py| - Test contacts/vias of different layers
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\item \verb|03_path_test.py| - Test different types of paths based off of the wire module
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\item \verb|03_ptx_test.py| - Test various sizes/fingers of PMOS and NMOS parameterized transistors
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\item \verb|03_wire_test.py| - Test different types of wires with different layers
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\item \verb|04_pinv_test.py| - Test various sizes of parameterized inverter
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\item \verb|04_nand_2_test.py| - Test various sizes of parameterized nand2
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\item \verb|04_nand_3_test.py| - Test various sizes of parameterized nand3
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\item \verb|04_nor_2_test.py| - Test various sizes of parameterized nor2
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\item \verb|04_wordline_driver_test.py| - Test a wordline\_driver array.
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\item \verb|05_array_test.py| - Test a small bit-cell array
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\item \verb|06_nand_decoder_test.py| - Test a dynamic NAND address decoder
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\item \verb|06_hierarchical_decoder_test.py| - Test a dynamic hierarchical address decoder
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\item \verb|07_tree_column_mux_test.py| - Test a small tree column mux.
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\item \verb|07_single_level_column_mux_test.py| - Test a small single level column mux.
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\item \verb|08_precharge_test.py| - Test a dynamically generated precharge array
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\item \verb|09_sense_amp_test.py| - Test a sense amplifier array
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\item \verb|10_write_driver_test.py| - Test a write driver array
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\item \verb|11_ms_flop_array_test.py| - Test a MS\_FF array
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\item \verb|13_control_logic_test.py| - Test the control logic module
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\item \verb|14_delay_chain_test.py| - Test a delay chain array
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\item \verb|15_tri_gate_array_test.py| - Test a tri-gate array
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\item \verb|16_replica_bitline_test.py| - Test a replica bitline
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\item \verb|19_bank_test.py| - Test a bank
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\item \verb|20_sram_test.py| - Test a complete small SRAM
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\item \verb|21_timing_sram_test.py| - Test timing of SRAM
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\item \verb|22_sram_func_test.py| - Test functionality of SRAM
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\end {itemize}
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Each unit test instantiates a small component and performs DRC/LVS. Automatic DRC/LVS inside OpenRAM is disabled so that Python unittest assertions can be used to track failures, errors, and successful tests as follows:
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\begin{verbatim}
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self.assertFalse(calibre.run_drc(a.cell_name,tempgds))
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self.assertFalse(calibre.run_lvs(a.cell_name,tempgds,tempspice))
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\end{verbatim}
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Each of these assertions will trigger a test failure. If there are
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problems with interpreting modified code due to syntax errors, the
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unit test framework will not capture this and it will result in an
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Error.
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\subsection{Usage}
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A regression script is provided to check all of the unit tests by running:
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\begin{verbatim}
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python tests/regress.py
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\end{verbatim}
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from the compiler directory located at: "OpenRAM/trunk/compiler/". Each individual test can be run by running:
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\begin{verbatim}
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python tests/{unit-test file}
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e.g. python tests/05_array_test.py
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\end{verbatim}
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from the compiler directory located at: "openram/trunk/compiler/". As an example, the unit tests all
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complete and provide the following output except for the final
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\verb|20_sram_test| which has 2 DRC violations:
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\begin{verbatim}
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[trunk/compiler]$ python tests/regress.py
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runTest (01_library_drc_test.library_drc_test) ... ok
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runTest (02_library_lvs_test.library_lvs_test) ... ok
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runTest (03_contact_test.contact_test) ... ok
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runTest (03_path_test.path_test) ... ok
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runTest (03_ptx_test.ptx_test) ... ok
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runTest (03_wire_test.wire_test) ... ok
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runTest (04_pinv_test.pinv_test) ... ok
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runTest (04_nand_2_test.nand_2_test) ... ok
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runTest (04_nand_3_test.nand_3_test) ... ok
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runTest (04_nor_2_test.nor_2_test) ... ok
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runTest (04_wordline_driver_test.wordline_driver_test) ... ok
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runTest (05_array_test.array_test) ... ok
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runTest (06_hierdecoder_test.hierdecoder_test) ... ok
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runTest (07_single_level_column_mux_test.single_level_column_mux_test) ... ok
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runTest (08_precharge_test.precharge_test) ... ok
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runTest (09_sense_amp_test.sense_amp_test) ... ok
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runTest (10_write_driver_test.write_driver_test) ... ok
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runTest (11_ms_flop_array_test.ms_flop_test) ... ok
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runTest (13_control_logic_test.control_logic_test) ... ok
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runTest (14_delay_chain_test.delay_chain_test) ... ok
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runTest (15_tri_gate_array_test.tri_gate_array_test) ... ok
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runTest (19_bank_test.bank_test) ... ok
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runTest (20_sram_test.sram_test) ... ok
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\end{verbatim}
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If there are any DRC/LVS violations during the test, all the summary,output,and error files
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will be generated in the technology directory's "openram\_temp" folder. One would view those
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files to determine the cause of the DRC/LVS violations.
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More information on the Python unittest framework is available at\\
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\begin{center}
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\url{http://docs.python.org/2/library/unittest.html}.
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\end{center}
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