mirror of https://github.com/VLSIDA/OpenRAM.git
612 lines
27 KiB
Python
612 lines
27 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2019 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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import datetime
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import debug
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from math import log
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from importlib import reload
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from vector import vector
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from globals import OPTS, print_time
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from design import design
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from verilog import verilog
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from lef import lef
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from sram_factory import factory
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class sram_base(design, verilog, lef):
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"""
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Dynamically generated SRAM by connecting banks to control logic. The
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number of banks should be 1 , 2 or 4
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"""
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def __init__(self, name, sram_config):
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design.__init__(self, name)
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lef.__init__(self, ["m1", "m2", "m3", "m4"])
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verilog.__init__(self)
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self.sram_config = sram_config
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sram_config.set_local_config(self)
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self.bank_insts = []
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if self.write_size:
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self.num_wmasks = int(self.word_size / self.write_size)
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else:
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self.num_wmasks = 0
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if not self.num_spare_cols:
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self.num_spare_cols = 0
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# For logical effort delay calculations.
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self.all_mods_except_control_done = False
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def add_pins(self):
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""" Add pins for entire SRAM. """
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for port in self.write_ports:
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for bit in range(self.word_size + self.num_spare_cols):
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self.add_pin("din{0}[{1}]".format(port, bit), "INPUT")
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for port in self.all_ports:
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for bit in range(self.addr_size):
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self.add_pin("addr{0}[{1}]".format(port, bit), "INPUT")
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# These are used to create the physical pins
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self.control_logic_inputs = []
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self.control_logic_outputs = []
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for port in self.all_ports:
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if port in self.readwrite_ports:
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self.control_logic_inputs.append(self.control_logic_rw.get_inputs())
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self.control_logic_outputs.append(self.control_logic_rw.get_outputs())
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elif port in self.write_ports:
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self.control_logic_inputs.append(self.control_logic_w.get_inputs())
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self.control_logic_outputs.append(self.control_logic_w.get_outputs())
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else:
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self.control_logic_inputs.append(self.control_logic_r.get_inputs())
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self.control_logic_outputs.append(self.control_logic_r.get_outputs())
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for port in self.all_ports:
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self.add_pin("csb{}".format(port), "INPUT")
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for port in self.readwrite_ports:
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self.add_pin("web{}".format(port), "INPUT")
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for port in self.all_ports:
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self.add_pin("clk{}".format(port), "INPUT")
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# add the optional write mask pins
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for port in self.write_ports:
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for bit in range(self.num_wmasks):
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self.add_pin("wmask{0}[{1}]".format(port, bit), "INPUT")
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for bit in range(self.num_spare_cols):
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self.add_pin("spare_wen{0}[{1}]".format(port, bit), "INPUT")
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for port in self.read_ports:
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for bit in range(self.word_size + self.num_spare_cols):
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self.add_pin("dout{0}[{1}]".format(port, bit), "OUTPUT")
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self.add_pin("vdd", "POWER")
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self.add_pin("gnd", "GROUND")
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def create_netlist(self):
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""" Netlist creation """
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start_time = datetime.datetime.now()
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# Must create the control logic before pins to get the pins
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self.add_modules()
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self.add_pins()
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self.create_modules()
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# This is for the lib file if we don't create layout
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self.width=0
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self.height=0
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if not OPTS.is_unit_test:
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print_time("Submodules", datetime.datetime.now(), start_time)
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def create_layout(self):
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""" Layout creation """
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start_time = datetime.datetime.now()
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self.place_instances()
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if not OPTS.is_unit_test:
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print_time("Placement", datetime.datetime.now(), start_time)
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start_time = datetime.datetime.now()
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self.route_layout()
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self.route_supplies()
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if not OPTS.is_unit_test:
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print_time("Routing", datetime.datetime.now(), start_time)
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self.add_lvs_correspondence_points()
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self.offset_all_coordinates()
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highest_coord = self.find_highest_coords()
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self.width = highest_coord[0]
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self.height = highest_coord[1]
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self.add_boundary(ll=vector(0, 0),
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ur=vector(self.width, self.height))
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start_time = datetime.datetime.now()
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# We only enable final verification if we have routed the design
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self.DRC_LVS(final_verification=OPTS.route_supplies)
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if not OPTS.is_unit_test:
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print_time("Verification", datetime.datetime.now(), start_time)
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def create_modules(self):
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debug.error("Must override pure virtual function.", -1)
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def route_supplies(self):
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""" Route the supply grid and connect the pins to them. """
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# Copy the pins to the top level
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# This will either be used to route or left unconnected.
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for inst in self.insts:
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self.copy_power_pins(inst, "vdd")
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self.copy_power_pins(inst, "gnd")
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if not OPTS.route_supplies:
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# Do not route the power supply (leave as must-connect pins)
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return
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grid_stack = set()
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try:
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from tech import power_grid
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grid_stack = power_grid
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except ImportError:
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# if no power_grid is specified by tech we use sensible defaults
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import tech
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if "m4" in tech.layer:
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# Route a M3/M4 grid
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grid_stack = self.m3_stack
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elif "m3" in tech.layer:
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grid_stack =("m3",)
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from supply_grid_router import supply_grid_router as router
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rtr=router(grid_stack, self)
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rtr.route()
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def compute_bus_sizes(self):
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""" Compute the independent bus widths shared between two and four bank SRAMs """
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# address size + control signals + one-hot bank select signals
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self.num_vertical_line = self.addr_size + self.control_size + log(self.num_banks, 2) + 1
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# data bus size
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self.num_horizontal_line = self.word_size
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self.vertical_bus_width = self.m2_pitch * self.num_vertical_line
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# vertical bus height depends on 2 or 4 banks
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self.data_bus_height = self.m3_pitch * self.num_horizontal_line
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self.data_bus_width = 2 * (self.bank.width + self.bank_to_bus_distance) + self.vertical_bus_width
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self.control_bus_height = self.m1_pitch * (self.control_size + 2)
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self.control_bus_width = self.bank.width + self.bank_to_bus_distance + self.vertical_bus_width
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self.supply_bus_height = self.m1_pitch * 2 # 2 for vdd/gnd placed with control bus
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self.supply_bus_width = self.data_bus_width
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# Sanity check to ensure we can fit the control logic above a single bank (0.9 is a hack really)
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debug.check(self.bank.width + self.vertical_bus_width > 0.9 * self.control_logic.width,
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"Bank is too small compared to control logic.")
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def add_busses(self):
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""" Add the horizontal and vertical busses """
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# Vertical bus
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# The order of the control signals on the control bus:
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self.control_bus_names = []
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for port in self.all_ports:
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self.control_bus_names[port] = ["clk_buf{}".format(port)]
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wen = "w_en{}".format(port)
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sen = "s_en{}".format(port)
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pen = "p_en_bar{}".format(port)
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if self.port_id[port] == "r":
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self.control_bus_names[port].extend([sen, pen])
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elif self.port_id[port] == "w":
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self.control_bus_names[port].extend([wen, pen])
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else:
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self.control_bus_names[port].extend([sen, wen, pen])
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self.vert_control_bus_positions = self.create_vertical_bus(layer="m2",
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pitch=self.m2_pitch,
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offset=self.vertical_bus_offset,
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names=self.control_bus_names[port],
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length=self.vertical_bus_height)
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self.addr_bus_names=["A{0}[{1}]".format(port, i) for i in range(self.addr_size)]
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self.vert_control_bus_positions.update(self.create_vertical_pin_bus(layer="m2",
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pitch=self.m2_pitch,
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offset=self.addr_bus_offset,
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names=self.addr_bus_names,
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length=self.addr_bus_height))
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self.bank_sel_bus_names = ["bank_sel{0}_{1}".format(port, i) for i in range(self.num_banks)]
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self.vert_control_bus_positions.update(self.create_vertical_pin_bus(layer="m2",
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pitch=self.m2_pitch,
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offset=self.bank_sel_bus_offset,
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names=self.bank_sel_bus_names,
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length=self.vertical_bus_height))
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# Horizontal data bus
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self.data_bus_names = ["DATA{0}[{1}]".format(port, i) for i in range(self.word_size)]
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self.data_bus_positions = self.create_horizontal_pin_bus(layer="m3",
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pitch=self.m3_pitch,
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offset=self.data_bus_offset,
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names=self.data_bus_names,
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length=self.data_bus_width)
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# Horizontal control logic bus
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# vdd/gnd in bus go along whole SRAM
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# FIXME: Fatten these wires?
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self.horz_control_bus_positions = self.create_horizontal_bus(layer="m1",
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pitch=self.m1_pitch,
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offset=self.supply_bus_offset,
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names=["vdd"],
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length=self.supply_bus_width)
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# The gnd rail must not be the entire width since we protrude the right-most vdd rail up for
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# the decoder in 4-bank SRAMs
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self.horz_control_bus_positions.update(self.create_horizontal_bus(layer="m1",
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pitch=self.m1_pitch,
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offset=self.supply_bus_offset + vector(0, self.m1_pitch),
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names=["gnd"],
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length=self.supply_bus_width))
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self.horz_control_bus_positions.update(self.create_horizontal_bus(layer="m1",
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pitch=self.m1_pitch,
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offset=self.control_bus_offset,
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names=self.control_bus_names[port],
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length=self.control_bus_width))
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def add_multi_bank_modules(self):
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""" Create the multibank address flops and bank decoder """
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from dff_buf_array import dff_buf_array
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self.msb_address = dff_buf_array(name="msb_address",
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rows=1,
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columns=self.num_banks / 2)
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self.add_mod(self.msb_address)
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if self.num_banks>2:
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self.msb_decoder = self.bank.decoder.pre2_4
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self.add_mod(self.msb_decoder)
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def add_modules(self):
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self.bitcell = factory.create(module_type=OPTS.bitcell)
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self.dff = factory.create(module_type="dff")
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# Create the address and control flops (but not the clk)
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self.row_addr_dff = factory.create("dff_array", module_name="row_addr_dff", rows=self.row_addr_size, columns=1)
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self.add_mod(self.row_addr_dff)
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if self.col_addr_size > 0:
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self.col_addr_dff = factory.create("dff_array", module_name="col_addr_dff", rows=1, columns=self.col_addr_size)
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self.add_mod(self.col_addr_dff)
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else:
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self.col_addr_dff = None
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self.data_dff = factory.create("dff_array", module_name="data_dff", rows=1, columns=self.word_size + self.num_spare_cols)
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self.add_mod(self.data_dff)
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if self.write_size:
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self.wmask_dff = factory.create("dff_array", module_name="wmask_dff", rows=1, columns=self.num_wmasks)
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self.add_mod(self.wmask_dff)
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if self.num_spare_cols:
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self.spare_wen_dff = factory.create("dff_array", module_name="spare_wen_dff", rows=1, columns=self.num_spare_cols)
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self.add_mod(self.spare_wen_dff)
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# Create the bank module (up to four are instantiated)
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self.bank = factory.create("bank", sram_config=self.sram_config, module_name="bank")
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self.add_mod(self.bank)
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# Create bank decoder
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if(self.num_banks > 1):
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self.add_multi_bank_modules()
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self.bank_count = 0
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# The control logic can resize itself based on the other modules.
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# Requires all other modules added before control logic.
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self.all_mods_except_control_done = True
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c = reload(__import__(OPTS.control_logic))
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self.mod_control_logic = getattr(c, OPTS.control_logic)
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# Create the control logic module for each port type
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if len(self.readwrite_ports)>0:
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self.control_logic_rw = self.mod_control_logic(num_rows=self.num_rows,
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words_per_row=self.words_per_row,
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word_size=self.word_size,
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spare_columns=self.num_spare_cols,
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sram=self,
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port_type="rw")
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self.add_mod(self.control_logic_rw)
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if len(self.writeonly_ports)>0:
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self.control_logic_w = self.mod_control_logic(num_rows=self.num_rows,
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words_per_row=self.words_per_row,
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word_size=self.word_size,
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spare_columns=self.num_spare_cols,
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sram=self,
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port_type="w")
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self.add_mod(self.control_logic_w)
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if len(self.readonly_ports)>0:
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self.control_logic_r = self.mod_control_logic(num_rows=self.num_rows,
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words_per_row=self.words_per_row,
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word_size=self.word_size,
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spare_columns=self.num_spare_cols,
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sram=self,
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port_type="r")
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self.add_mod(self.control_logic_r)
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def create_bank(self, bank_num):
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""" Create a bank """
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self.bank_insts.append(self.add_inst(name="bank{0}".format(bank_num),
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mod=self.bank))
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temp = []
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for port in self.read_ports:
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for bit in range(self.word_size + self.num_spare_cols):
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temp.append("dout{0}[{1}]".format(port, bit))
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for port in self.all_ports:
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temp.append("rbl_bl{0}".format(port))
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for port in self.write_ports:
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for bit in range(self.word_size + self.num_spare_cols):
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temp.append("bank_din{0}[{1}]".format(port, bit))
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for port in self.all_ports:
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for bit in range(self.bank_addr_size):
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temp.append("a{0}[{1}]".format(port, bit))
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if(self.num_banks > 1):
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for port in self.all_ports:
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temp.append("bank_sel{0}[{1}]".format(port, bank_num))
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for port in self.read_ports:
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temp.append("s_en{0}".format(port))
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for port in self.all_ports:
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temp.append("p_en_bar{0}".format(port))
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for port in self.write_ports:
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temp.append("w_en{0}".format(port))
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for bit in range(self.num_wmasks):
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temp.append("bank_wmask{}[{}]".format(port, bit))
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for bit in range(self.num_spare_cols):
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temp.append("bank_spare_wen{0}[{1}]".format(port, bit))
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for port in self.all_ports:
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temp.append("wl_en{0}".format(port))
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temp.extend(["vdd", "gnd"])
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self.connect_inst(temp)
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return self.bank_insts[-1]
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def place_bank(self, bank_inst, position, x_flip, y_flip):
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""" Place a bank at the given position with orientations """
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# x_flip == 1 --> no flip in x_axis
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# x_flip == -1 --> flip in x_axis
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# y_flip == 1 --> no flip in y_axis
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# y_flip == -1 --> flip in y_axis
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# x_flip and y_flip are used for position translation
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if x_flip == -1 and y_flip == -1:
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bank_rotation = 180
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else:
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bank_rotation = 0
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if x_flip == y_flip:
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bank_mirror = "R0"
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elif x_flip == -1:
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bank_mirror = "MX"
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elif y_flip == -1:
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bank_mirror = "MY"
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else:
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bank_mirror = "R0"
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bank_inst.place(offset=position,
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mirror=bank_mirror,
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rotate=bank_rotation)
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return bank_inst
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def create_row_addr_dff(self):
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""" Add all address flops for the main decoder """
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insts = []
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for port in self.all_ports:
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insts.append(self.add_inst(name="row_address{}".format(port),
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mod=self.row_addr_dff))
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# inputs, outputs/output/bar
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inputs = []
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outputs = []
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for bit in range(self.row_addr_size):
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inputs.append("addr{}[{}]".format(port, bit + self.col_addr_size))
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outputs.append("a{}[{}]".format(port, bit + self.col_addr_size))
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self.connect_inst(inputs + outputs + ["clk_buf{}".format(port), "vdd", "gnd"])
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return insts
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def create_col_addr_dff(self):
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""" Add and place all address flops for the column decoder """
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insts = []
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for port in self.all_ports:
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insts.append(self.add_inst(name="col_address{}".format(port),
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mod=self.col_addr_dff))
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# inputs, outputs/output/bar
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inputs = []
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outputs = []
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for bit in range(self.col_addr_size):
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inputs.append("addr{}[{}]".format(port, bit))
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outputs.append("a{}[{}]".format(port, bit))
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self.connect_inst(inputs + outputs + ["clk_buf{}".format(port), "vdd", "gnd"])
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return insts
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def create_data_dff(self):
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""" Add and place all data flops """
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insts = []
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for port in self.all_ports:
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if port in self.write_ports:
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insts.append(self.add_inst(name="data_dff{}".format(port),
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mod=self.data_dff))
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else:
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insts.append(None)
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continue
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|
# inputs, outputs/output/bar
|
|
inputs = []
|
|
outputs = []
|
|
for bit in range(self.word_size + self.num_spare_cols):
|
|
inputs.append("din{}[{}]".format(port, bit))
|
|
outputs.append("bank_din{}[{}]".format(port, bit))
|
|
|
|
self.connect_inst(inputs + outputs + ["clk_buf{}".format(port), "vdd", "gnd"])
|
|
|
|
return insts
|
|
|
|
def create_wmask_dff(self):
|
|
""" Add and place all wmask flops """
|
|
insts = []
|
|
for port in self.all_ports:
|
|
if port in self.write_ports:
|
|
insts.append(self.add_inst(name="wmask_dff{}".format(port),
|
|
mod=self.wmask_dff))
|
|
else:
|
|
insts.append(None)
|
|
continue
|
|
|
|
# inputs, outputs/output/bar
|
|
inputs = []
|
|
outputs = []
|
|
for bit in range(self.num_wmasks):
|
|
inputs.append("wmask{}[{}]".format(port, bit))
|
|
outputs.append("bank_wmask{}[{}]".format(port, bit))
|
|
|
|
self.connect_inst(inputs + outputs + ["clk_buf{}".format(port), "vdd", "gnd"])
|
|
|
|
return insts
|
|
|
|
def create_spare_wen_dff(self):
|
|
""" Add all spare write enable flops """
|
|
insts = []
|
|
for port in self.all_ports:
|
|
if port in self.write_ports:
|
|
insts.append(self.add_inst(name="spare_wen_dff{}".format(port),
|
|
mod=self.spare_wen_dff))
|
|
else:
|
|
insts.append(None)
|
|
continue
|
|
|
|
# inputs, outputs/output/bar
|
|
inputs = []
|
|
outputs = []
|
|
for bit in range(self.num_spare_cols):
|
|
inputs.append("spare_wen{}[{}]".format(port, bit))
|
|
outputs.append("bank_spare_wen{}[{}]".format(port, bit))
|
|
|
|
self.connect_inst(inputs + outputs + ["clk_buf{}".format(port), "vdd", "gnd"])
|
|
|
|
return insts
|
|
|
|
def create_control_logic(self):
|
|
""" Add control logic instances """
|
|
|
|
insts = []
|
|
for port in self.all_ports:
|
|
if port in self.readwrite_ports:
|
|
mod = self.control_logic_rw
|
|
elif port in self.write_ports:
|
|
mod = self.control_logic_w
|
|
else:
|
|
mod = self.control_logic_r
|
|
|
|
insts.append(self.add_inst(name="control{}".format(port), mod=mod))
|
|
|
|
# Inputs
|
|
temp = ["csb{}".format(port)]
|
|
if port in self.readwrite_ports:
|
|
temp.append("web{}".format(port))
|
|
temp.append("clk{}".format(port))
|
|
temp.append("rbl_bl{}".format(port))
|
|
|
|
# Outputs
|
|
if port in self.read_ports:
|
|
temp.append("s_en{}".format(port))
|
|
if port in self.write_ports:
|
|
temp.append("w_en{}".format(port))
|
|
temp.append("p_en_bar{}".format(port))
|
|
temp.extend(["wl_en{}".format(port), "clk_buf{}".format(port), "vdd", "gnd"])
|
|
self.connect_inst(temp)
|
|
|
|
return insts
|
|
|
|
def sp_write(self, sp_name, lvs_netlist=False):
|
|
# Write the entire spice of the object to the file
|
|
############################################################
|
|
# Spice circuit
|
|
############################################################
|
|
sp = open(sp_name, 'w')
|
|
|
|
sp.write("**************************************************\n")
|
|
sp.write("* OpenRAM generated memory.\n")
|
|
sp.write("* Words: {}\n".format(self.num_words))
|
|
sp.write("* Data bits: {}\n".format(self.word_size))
|
|
sp.write("* Banks: {}\n".format(self.num_banks))
|
|
sp.write("* Column mux: {}:1\n".format(self.words_per_row))
|
|
sp.write("**************************************************\n")
|
|
# This causes unit test mismatch
|
|
# sp.write("* Created: {0}\n".format(datetime.datetime.now()))
|
|
# sp.write("* User: {0}\n".format(getpass.getuser()))
|
|
# sp.write(".global {0} {1}\n".format(spice["vdd_name"],
|
|
# spice["gnd_name"]))
|
|
usedMODS = list()
|
|
self.sp_write_file(sp, usedMODS, lvs_netlist=lvs_netlist)
|
|
del usedMODS
|
|
sp.close()
|
|
|
|
def lvs_write(self, sp_name):
|
|
self.sp_write(sp_name, lvs_netlist=True)
|
|
|
|
def get_wordline_stage_efforts(self, inp_is_rise=True):
|
|
"""Get the all the stage efforts for each stage in the path from clk_buf to a wordline"""
|
|
stage_effort_list = []
|
|
|
|
# Clk_buf originates from the control logic so only the bank is related to the wordline path
|
|
# No loading on the wordline other than in the bank.
|
|
external_wordline_cout = 0
|
|
stage_effort_list += self.bank.determine_wordline_stage_efforts(external_wordline_cout, inp_is_rise)
|
|
|
|
return stage_effort_list
|
|
|
|
def get_wl_en_cin(self):
|
|
"""Gets the capacitive load the of clock (clk_buf) for the sram"""
|
|
# Only the wordline drivers within the bank use this signal
|
|
return self.bank.get_wl_en_cin()
|
|
|
|
def get_w_en_cin(self):
|
|
"""Gets the capacitive load the of write enable (w_en) for the sram"""
|
|
# Only the write drivers within the bank use this signal
|
|
return self.bank.get_w_en_cin()
|
|
|
|
def get_p_en_bar_cin(self):
|
|
"""Gets the capacitive load the of precharge enable (p_en_bar) for the sram"""
|
|
# Only the precharges within the bank use this signal
|
|
return self.bank.get_p_en_bar_cin()
|
|
|
|
def get_clk_bar_cin(self):
|
|
"""Gets the capacitive load the of clock (clk_buf_bar) for the sram"""
|
|
# As clk_buf_bar is an output of the control logic. The cap for that module is not determined here.
|
|
# Only the precharge cells use this signal (other than the control logic)
|
|
return self.bank.get_clk_bar_cin()
|
|
|
|
def get_sen_cin(self):
|
|
"""Gets the capacitive load the of sense amp enable for the sram"""
|
|
# Only the sense_amps use this signal (other than the control logic)
|
|
return self.bank.get_sen_cin()
|
|
|
|
def get_dff_clk_buf_cin(self):
|
|
"""Get the relative capacitance of the clk_buf signal.
|
|
Does not get the control logic loading but everything else"""
|
|
total_cin = 0
|
|
total_cin += self.row_addr_dff.get_clk_cin()
|
|
total_cin += self.data_dff.get_clk_cin()
|
|
if self.col_addr_size > 0:
|
|
total_cin += self.col_addr_dff.get_clk_cin()
|
|
return total_cin
|