mirror of https://github.com/VLSIDA/OpenRAM.git
215 lines
7.6 KiB
Python
215 lines
7.6 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2021 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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from openram.base import design
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from openram.sram_factory import factory
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from openram.base import vector
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from openram.tech import layer, drc
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class rom_address_control_buf(design):
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"""
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Takes the input address lines and creates the address and address bar lines for the decoder.
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Adds control logic for the precharge cycle so that all address lines are high before the read cycle
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"""
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def __init__(self, size, name="", route_layer="m1", add_wells=False):
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self.route_layer = route_layer
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self.add_wells = add_wells
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self.size = size
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if "li" in layer:
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self.inv_layer = "li"
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else:
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self.inv_layer = "m1"
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super().__init__(name)
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self.create_netlist()
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self.create_layout()
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def create_netlist(self):
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self.create_modules()
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self.add_pins()
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self.create_instances()
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def create_layout(self):
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self.width = self.cell.height * 2
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self.height = self.inv.width + 2 * self.nand.width
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self.setup_layout_constants()
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self.place_instances()
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# self.place_vias()
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self.route_gates()
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self.route_sources()
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self.add_boundary()
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def create_modules(self):
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# self.inv1_mod = factory.create(module_type="pinv", module_name="inv_array_end_mod", height=self.inv_size, add_wells=False)
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self.inv = factory.create(module_type="pinv_dec", module_name="inv_array_mod", add_wells=False, size=self.size)
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# self.end_inv = factory.create(module_type="pinv", module_name="inv_array_end_mod", size=self.size, add_wells=True)
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self.nand = factory.create(module_type="nand2_dec", height=self.inv.height)
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# For layout constants
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self.cell = factory.create(module_type="rom_base_cell")
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def add_pins(self):
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self.add_pin("A_in", "INPUT")
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self.add_pin("A_out", "INOUT")
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self.add_pin("Abar_out", "OUTPUT")
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self.add_pin("clk", "INPUT")
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self.add_pin("vdd", "POWER")
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self.add_pin("gnd", "GROUND")
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def create_instances(self):
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name = "XinvAbar"
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self.inv_inst = self.add_inst(name=name, mod=self.inv)
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inst_A = "A_in"
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inst_Z = "Abar_internal"
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self.connect_inst([inst_A, inst_Z, "vdd", "gnd"])
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name = "Xnand_addr"
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self.addr_nand = self.add_inst(name=name, mod=self.nand)
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inst_A = "clk"
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inst_B = "Abar_internal"
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inst_Z = "A_out"
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self.connect_inst([inst_A, inst_B, inst_Z, "vdd", "gnd"])
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name = "Xnand_addr_bar"
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self.addr_bar_nand = self.add_inst(name=name, mod=self.nand)
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inst_A = "clk"
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inst_B = "A_out"
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inst_Z = "Abar_out"
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self.connect_inst([inst_A, inst_B, inst_Z, "vdd", "gnd"])
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def setup_layout_constants(self):
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self.route_width = drc["minwidth_{}".format(self.route_layer)]
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self.interconnect_width = drc["minwidth_{}".format(self.inv_layer)]
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def place_instances(self):
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self.inv_inst.place(offset=vector(self.inv_inst.height,0), rotate=90)
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self.addr_nand.place(offset=vector(self.addr_nand.height , self.inv_inst.width + self.route_width ), rotate=90)
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self.addr_bar_nand.place(offset=vector( self.addr_bar_nand.height, self.addr_nand.width + self.inv_inst.width + self.route_width), rotate=90)
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def route_gates(self):
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clk1_pin = self.addr_nand.get_pin("A")
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clk2_pin = self.addr_bar_nand.get_pin("A")
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# self.add_label("HERE I AM", "poly", clk_pins.cl())
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Abar_out = self.addr_bar_nand.get_pin("Z")
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A_out = self.addr_nand.get_pin("Z")
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Abar_in = self.addr_nand.get_pin("B")
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Abar_int_out = self.inv_inst.get_pin("Z")
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Aint_in = self.addr_bar_nand.get_pin("B")
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A_in = self.inv_inst.get_pin("A")
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# Find the center of the pmos poly/gate
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poly_right = clk1_pin.cx() + self.poly_enclose_contact + 0.5 * self.contact_width
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ppoly_center = poly_right - 0.7 * self.poly_width
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contact_offset = vector(ppoly_center, clk2_pin.cy())
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# Route the two shared clk inputs together by connecting poly
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self.add_segment_center("poly", contact_offset, vector(ppoly_center, A_out.cy()))
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clk_offset = vector(clk2_pin.cx(), self.addr_nand.uy())
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self.add_layout_pin_rect_center("clk", offset=clk_offset, layer=self.route_layer)
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self.add_via_stack_center(from_layer=self.inv_layer, to_layer=self.route_layer, offset=self.addr_bar_nand.get_pin("A").center())
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self.add_segment_center(self.route_layer, clk_offset, vector(clk_offset.x, clk2_pin.cy()))
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# Route first NAND output to second NAND input
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start = A_out.center()
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end = Aint_in.center()
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self.add_path("m2", [start, end])
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self.add_via_stack_center(Aint_in.center(), self.inv_layer, "m2")
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self.add_via_stack_center(A_out.center(), self.inv_layer, "m2")
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# Route first NAND to output pin
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self.add_segment_center("m2", end, vector(end.x, self.addr_bar_nand.uy()))
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self.add_layout_pin_rect_center("A_out", offset=vector(end.x, self.addr_bar_nand.uy() - 0.5 * self.m2_width), layer="m2")
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# Route second NAND to output pin
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self.add_via_stack_center(Abar_out.center(), self.inv_layer, "m2")
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self.add_segment_center("m2", Abar_out.center(), vector(Abar_out.cx(), self.addr_bar_nand.uy()))
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self.add_layout_pin_rect_center("Abar_out", offset=vector(Abar_out.cx(), self.addr_bar_nand.uy() - 0.5 * self.m2_width), layer="m2")
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# Route inverter output to NAND
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end = vector(Abar_int_out.cx(), Abar_in.cy() + 0.5 * self.interconnect_width)
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self.add_segment_center(self.inv_layer, Abar_int_out.center(), end)
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self.copy_layout_pin(self.inv_inst, "A", "A_in")
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def route_sources(self):
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self.copy_layout_pin(self.addr_nand, "vdd")
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self.copy_layout_pin(self.addr_bar_nand, "vdd")
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self.copy_layout_pin(self.inv_inst, "vdd")
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self.copy_layout_pin(self.addr_bar_nand, "gnd")
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self.copy_layout_pin(self.addr_nand, "gnd")
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self.copy_layout_pin(self.inv_inst, "gnd")
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""" Add n/p well taps to the layout and connect to supplies """
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source_pin = self.inv_inst.get_pin("vdd")
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gnd_pin = self.inv_inst.get_pin("gnd")
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left_edge = self.inv_inst.get_pin("Z").cx() - 2 * self.contact_width - 2 * self.active_contact_to_gate - 4 * self.active_enclose_contact - self.poly_width - self.active_space
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contact_pos = vector(left_edge, source_pin.cy())
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self.add_via_center(layers=self.active_stack,
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offset=contact_pos,
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implant_type="n",
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well_type="n")
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self.add_via_stack_center(offset=contact_pos,
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from_layer=self.active_stack[2],
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to_layer=self.route_layer)
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contact_pos = vector(left_edge, gnd_pin.cy())
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self.add_via_center(layers=self.active_stack,
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offset=contact_pos,
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implant_type="p",
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well_type="p")
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self.add_via_stack_center(offset=contact_pos,
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from_layer=self.active_stack[2],
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to_layer=self.route_layer)
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