OpenRAM

An open-source static random access memory (SRAM) compiler.

What is OpenRAM?

OpenRAM is an award winning open-source Python framework to create the layout, netlists, timing and power models, placement and routing models, and other views necessary to use SRAMs in ASIC design. OpenRAM supports integration in both commercial and open-source flows with both predictive and fabricable technologies.

Documentation

Please take a look at our presentation We have created a detailed presentation that serves as our documentation. This is the most up-to-date information, so please let us know if you see things that need to be fixed.

Basic Setup

Docker

We have a docker setup to run OpenRAM.

Dependencies

The OpenRAM compiler has very few dependencies:

• Ngspice 34 (or later) or HSpice I-2013.12-1 (or later) or CustomSim 2017 (or later) or Xyce 7.4 (or later)
• Python 3.6 or higher
• Various Python packages (pip install -r requirements.txt)
• Git

If you want to perform DRC and LVS, you will need either:

• Calibre (for FreePDK45)
• Magic 8.3.197 or newer
• Netgen 1.5.195 or newer

You must set two environment variables:

• OPENRAM_HOME should point to the compiler source directory.
• OPENERAM_TECH should point to one or more root technology directories (colon separated).

Environment

For example add this to your .bashrc:

  export OPENRAM_HOME="$HOME/openram/compiler"
  export OPENRAM_TECH="$HOME/openram/technology"

You may also wish to add OPENRAM_HOME to your PYTHONPATH:

  export PYTHONPATH="$PYTHONPATH:$OPENRAM_HOME"

We include the tech files necessary for SCMOS SCN4M_SUBM, FreePDK45, and Sky130. The SCMOS spice models, however, are generic and should be replaced with foundry models. You may get the entire FreePDK45 PDK here.

To install Sky130, simply run:

make install

Basic Usage

Once you have defined the environment, you can run OpenRAM from the command line using a single configuration file written in Python.

For example, create a file called myconfig.py specifying the following parameters for your memory:

# Data word size
word_size = 2
# Number of words in the memory
num_words = 16

# Technology to use in $OPENRAM_TECH
tech_name = "scn4m_subm"

# You can use the technology nominal corner only
nominal_corner_only = True
# Or you can specify particular corners
# Process corners to characterize
# process_corners = ["SS", "TT", "FF"]
# Voltage corners to characterize
# supply_voltages = [ 3.0, 3.3, 3.5 ]
# Temperature corners to characterize
# temperatures = [ 0, 25 100]

# Output directory for the results
output_path = "temp"
# Output file base name
output_name = "sram_{0}_{1}_{2}".format(word_size,num_words,tech_name)

# Disable analytical models for full characterization (WARNING: slow!)
# analytical_delay = False

You can then run OpenRAM by executing:

python3 $OPENRAM_HOME/openram.py myconfig

You can see all of the options for the configuration file in $OPENRAM_HOME/options.py

To run designs in Docker, it is suggested to use, for example:

cd openram/macros
make example_config_scn4m_subm

Unit Tests

Regression testing performs a number of tests for all modules in OpenRAM. From the unit test directory ($OPENRAM_HOME/tests), use the following command to run all regression tests:

cd openram/compiler/tests
make regress

To run a specific test:

ce openram/compiler/tests
make 05_bitcell_array_test

To increase the verbosity of the test, add one (or more) -v options and pass it as an argument to OpenRAM:

make 05_bitcell_array_test ARGS="-v -t scn4m_subm"

To specify a particular technology use "-t " such as "-t freepdk45". The default for a unit test is scn4m_subm. The default for openram.py is specified in the configuration file.

Get Involved

• Port it to a new technology.
• Report bugs by submitting Github issues.
• Develop new features (see how to contribute)
• Submit code/fixes using a Github pull request
• Follow our project.
• Read and cite our ICCAD paper

Further Help

• Additional hints
• Documentation
• OpenRAM Slack Workspace
• OpenRAM Users Group (subscribe here)
• OpenRAM Developers Group (subscribe here)

License

OpenRAM is licensed under the BSD 3-clause License.

Contributors & Acknowledgment

• Matthew Guthaus from VLSIDA created the OpenRAM project and is the lead architect.
• James Stine from VLSIARCH co-founded the project.
• Many students: Hunter Nichols, Michael Grimes, Jennifer Sowash, Yusu Wang, Joey Kunzler, Jesse Cirimelli-Low, Samira Ataei, Bin Wu, Brian Chen, Jeff Butera

If I forgot to add you, please let me know!

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