mirror of https://github.com/VLSIDA/OpenRAM.git
29 lines
525 B
Python
29 lines
525 B
Python
word_size = 64
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num_words = 64
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num_rw_ports = 1
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num_r_ports = 0
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num_w_ports = 0
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num_banks = 1
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words_per_row = 1
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spice_name = "hspice"
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tech_name = "freepdk45"
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process_corners = ["TT"]
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supply_voltages = [1.0]
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temperatures = [25]
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route_supplies = True
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perimeter_pins = False
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check_lvsdrc = True
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nominal_corner_only = True
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load_scales = [0.5]
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slew_scales = [0.5]
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use_pex = False
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analytical_delay = False
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output_name = "sram_w_{0}_{1}_{2}".format(word_size, num_words, tech_name)
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output_path = "macro/{}".format(output_name)
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