This website requires JavaScript.
Explore
Help
Sign In
luke
/
OpenRAM
Watch
1
Star
0
Fork
0
mirror of
https://github.com/VLSIDA/OpenRAM.git
synced
2026-08-29 17:39:02 +02:00
Code
Issues
Packages
Projects
Releases
Wiki
Activity
Files
f55b57033d467d1b04b37a5229051ca78b83a547
OpenRAM
/
compiler
/
verify
T
History
mrg
9d9f0fddf0
Only do total DRC count.
2020-12-15 13:00:20 -08:00
..
__init__.py
Temp comment Magic GDS filter code.
2020-11-10 13:37:18 -08:00
assura.py
Output DRC and LVS run files to output directory.
2020-11-09 11:12:31 -08:00
calibre.py
Fix copy gds/sp error with new relative paths
2020-12-11 10:22:35 -08:00
magic.py
Only do total DRC count.
2020-12-15 13:00:20 -08:00
none.py
Use readspice to define ports from sp netlist in Magic extract.
2020-11-10 17:06:24 -08:00
run_script.py
Decrease verbosity of script output
2020-12-01 17:12:17 -08:00