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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 09:30:38 +02:00
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f3f19aeeeb93e5e87f75056da9ba4ca539b140a3
OpenRAM/compiler/bitcells
T
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Hunter Nichols 16e658726e When determining bitline names, added a technology check for sky130.
2021-06-16 17:04:02 -07:00
..
bitcell_1port.py
Update copyright year.
2021-01-22 11:23:28 -08:00
bitcell_2port.py
Update copyright year.
2021-01-22 11:23:28 -08:00
bitcell_base.py
When determining bitline names, added a technology check for sky130.
2021-06-16 17:04:02 -07:00
col_cap_bitcell_1port.py
Update copyright year.
2021-01-22 11:23:28 -08:00
col_cap_bitcell_2port.py
Update copyright year.
2021-01-22 11:23:28 -08:00
dummy_bitcell_1port.py
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2021-01-22 11:23:28 -08:00
dummy_bitcell_2port.py
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2021-01-22 11:23:28 -08:00
dummy_pbitcell.py
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2021-01-22 11:23:28 -08:00
pbitcell.py
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2021-01-22 11:23:28 -08:00
replica_bitcell_1port.py
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2021-01-22 11:23:28 -08:00
replica_bitcell_2port.py
Update copyright year.
2021-01-22 11:23:28 -08:00
replica_pbitcell.py
Update copyright year.
2021-01-22 11:23:28 -08:00
row_cap_bitcell_1port.py
Update copyright year.
2021-01-22 11:23:28 -08:00
row_cap_bitcell_2port.py
Update copyright year.
2021-01-22 11:23:28 -08:00
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